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[209.85.219.178]) by smtp.gmail.com with ESMTPSA id b1sm5609148qkk.117.2021.03.19.16.10.56 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Mar 2021 16:10:56 -0700 (PDT) Received: by mail-yb1-f178.google.com with SMTP id c131so7911215ybf.7 for ; Fri, 19 Mar 2021 16:10:56 -0700 (PDT) X-Received: by 2002:a25:ab54:: with SMTP id u78mr10033101ybi.276.1616195455835; Fri, 19 Mar 2021 16:10:55 -0700 (PDT) MIME-Version: 1.0 References: <1616158446-19290-1-git-send-email-kalyan_t@codeaurora.org> In-Reply-To: <1616158446-19290-1-git-send-email-kalyan_t@codeaurora.org> From: Doug Anderson Date: Fri, 19 Mar 2021 16:10:43 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [v1] drm/msm/disp/dpu1: fix display underruns during modeset. To: Kalyan Thota Cc: y@qualcomm.com, dri-devel , linux-arm-msm , freedreno , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , Rob Clark , mkrishn@codeaurora.org, Stephen Boyd Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Fri, Mar 19, 2021 at 5:54 AM Kalyan Thota wrote: > > During crtc disable, display perf structures are reset to 0 > which includes state varibles which are immutable. On crtc > enable, we use the same structures and they don't refelect > the actual values > > 1) Fix is to avoid updating the state structures during disable. > 2) Reset the perf structures during atomic check when there is no > modeset enable. > > Signed-off-by: Kalyan Thota > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 1 - > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 1 + > 2 files changed, 1 insertion(+), 1 deletion(-) I think Stephen was the one who originally noticed this and reported it, so: Reported-by: Stephen Boyd Seems to work for me. I got into the state where it was doing a modeset at reboot (could see the underflow color for a period of time when this happened). I added your patch and it looks better. Tested-by: Douglas Anderson