Received: by 2002:a05:6a10:9848:0:0:0:0 with SMTP id x8csp2637641pxf; Sun, 21 Mar 2021 01:38:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAbVJL9rQaZZSgEAfMAdA1sW3rRXfKZTmg3oV3kjj89y5EMKnVJ2oy4s29NMr9x1KGeo0N X-Received: by 2002:a05:6402:57:: with SMTP id f23mr19022290edu.323.1616315934720; Sun, 21 Mar 2021 01:38:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616315934; cv=none; d=google.com; s=arc-20160816; b=tWa+duyDNG96itXkhoG1C05N82F3MyVKyizjwTj4JzT0mJtQHFp6C4esOCg6cHvpkK thnI9krVKmhTkLXi62LwbyoQS6+yQlcR7HD2hcUJ24d48Djhyc5MWhFJUJqqKQOv3IFs UbFzWdeExyn6yQffP1ts4yMTAbQ5fEux0xH/CZQX7r0olNnn7LruK7h0kS4g4+zin891 fOKT+hvxQWT9aT9bDLTjwFtv1x5SYjxcpVY4k6/y7E0tAcwQz2zsikLZNT1NVWtDefbG JLoSkJRpiEWXvs28pqlduSkiUQFOCvrfEf5xG4AmtC29xMdD0Plgq2aIbCw1hlhtUpXQ grmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=4iHbx0OA+Ob50g3/bpCToNOi+mNatCRmmXL44JodfHw=; b=U7e0BriE6LEhN3aDRsCfglWhEx+hUCcO4OV05LFtYClv3jGgsPthlTZg2iCm7mdmov RhKt1n55evVA9+9WOAPA0p9dEQNr0ef+7qC4OB1J0JOSNzuN6EMt3DgZv2mxtwv6Lc/K 6TT3YJYS9wRDpWANnIFrZ/hVTNZ8vUPr5ymU8iQ3AdKiP27CZhkyDQp23LAQ5eMHKmDW Nvc2rr5zEGdSQZh+xF7l6x/u3SgFQTVZiYOO2+1pA3LbdI0nRtrB7FojvPlK3K8Uyflx NJr0k92MWQqLFwUyG9e1AwyHr6OspLswVmngOclZ40msHVhRdglHD8YcAC2J+Igdaid1 z/Jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@libero.it header.s=s2021 header.b="JQ1/P5Jy"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=libero.it Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z31si8302439ede.226.2021.03.21.01.38.32; Sun, 21 Mar 2021 01:38:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@libero.it header.s=s2021 header.b="JQ1/P5Jy"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=libero.it Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230104AbhCUIcm (ORCPT + 99 others); Sun, 21 Mar 2021 04:32:42 -0400 Received: from smtp-17.italiaonline.it ([213.209.10.17]:32853 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230107AbhCUIcV (ORCPT ); Sun, 21 Mar 2021 04:32:21 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id NtVMlAZljtpGHNtVTlqmNc; Sun, 21 Mar 2021 09:32:20 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1616315540; bh=4iHbx0OA+Ob50g3/bpCToNOi+mNatCRmmXL44JodfHw=; h=From; b=JQ1/P5JyB/0wSrJH1pjLOHp0TkfvPK16xXkUnYwrDyx0+c+2OlilGjMfCM9ydgjbB 4iRIPnG1+3eTp3Tg3YpioRnbiyYNh4vlFdRFFta/os89Izlwx9qmj3dNlW25Axh5ys C2Hz7XiWx1HNfP+BX/TqKlHwNFEQwyqQ2DLVS4m4Sir8oRsupiibhitZ6qYmgc+MSp ta3NzM5wQ0QNy00yGpZDNzuy0OfK+x6MQGG199KnWeQCR0CNAAjBnf8nfpby8mqSkC aGwluPZGXXRkudZUsKsfnGJchRJ4Lj82D9yn5DJYZL5ZPO9BxDTnbbp8IYRrcaxaoA gZ/tlqeEydVgQ== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=60570494 cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=-grNfQwawjkoE-hAE8wA:9 a=+jEqtf1s3R9VXZ0wqowq2kgwd+I=:19 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Dario Binacchi , Daniel Vetter , David Airlie , Jyri Sarha , Tomi Valkeinen , dri-devel@lists.freedesktop.org Subject: [PATCH v2 1/3] drm/tilcdc: rename req_rate to pclk_rate Date: Sun, 21 Mar 2021 09:31:51 +0100 Message-Id: <20210321083153.2810-2-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210321083153.2810-1-dariobin@libero.it> References: <20210321083153.2810-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfGYuO55UauguG8LZNRcmyHroAcDp+2JpRvAFwgtJL1cKoBrLU9V2fNiObqSUPbu4ZYo8PS28SddIoww3mb/t2bWNQMSdoY1uMv+6l99790V1o0u5/Z+c Eacui1h0yJDRDk9cfJ4aOSUaeTMeb6tFKScfpOY7cJgTuy7f2DbDyECbWrcDffVfRmCOgDcpl/uPnajgsnTofFIkrTZCVL0iauZeCaCa7SV3q2G8OtojHLo/ 1A/WPIQ6bKBX5byBSwJsJJBX4wj6OuwNXc++i4weGDAjlEszd2LndS2hdHwRreuuM5dC/ewFysrCYFnMv7u68YfGZ3pVvGVh6jd8TeA/cD9mafh9irH4feCg QhU5NS5uxCBlLXs/PXxDR93C66VDv2p7gX+G5TD0h+ZcVpbogpzXhKbY0l/LXmoF/KFLS1wc Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The req_rate name is a little misleading, so let's rename to pclk_rate (pixel clock rate). Signed-off-by: Dario Binacchi --- Changes in v2: - The patch has been added in version 2. drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c index 30213708fc99..aeec5786617d 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -203,18 +203,18 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) struct drm_device *dev = crtc->dev; struct tilcdc_drm_private *priv = dev->dev_private; struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); - unsigned long clk_rate, real_rate, req_rate; + unsigned long clk_rate, real_rate, pclk_rate; unsigned int clkdiv; int ret; clkdiv = 2; /* first try using a standard divider of 2 */ /* mode.clock is in KHz, set_rate wants parameter in Hz */ - req_rate = crtc->mode.clock * 1000; + pclk_rate = crtc->mode.clock * 1000; - ret = clk_set_rate(priv->clk, req_rate * clkdiv); + ret = clk_set_rate(priv->clk, pclk_rate * clkdiv); clk_rate = clk_get_rate(priv->clk); - if (ret < 0 || tilcdc_pclk_diff(req_rate, clk_rate) > 5) { + if (ret < 0 || tilcdc_pclk_diff(pclk_rate, clk_rate) > 5) { /* * If we fail to set the clock rate (some architectures don't * use the common clock framework yet and may not implement @@ -229,7 +229,7 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) return; } - clkdiv = DIV_ROUND_CLOSEST(clk_rate, req_rate); + clkdiv = DIV_ROUND_CLOSEST(clk_rate, pclk_rate); /* * Emit a warning if the real clock rate resulting from the @@ -238,7 +238,7 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) * 5% is an arbitrary value - LCDs are usually quite tolerant * about pixel clock rates. */ - real_rate = clkdiv * req_rate; + real_rate = clkdiv * pclk_rate; if (tilcdc_pclk_diff(clk_rate, real_rate) > 5) { dev_warn(dev->dev, -- 2.17.1