Received: by 2002:a05:6a10:9848:0:0:0:0 with SMTP id x8csp3577387pxf; Mon, 22 Mar 2021 09:36:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz1vuNYq+yjhKte5tQyVkg4W7E3x1QoQPqoHcN/eMX1NdFDmnKyal2lH1hwMfv9yP2lH92p X-Received: by 2002:a17:906:78d:: with SMTP id l13mr658495ejc.97.1616430998330; Mon, 22 Mar 2021 09:36:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616430998; cv=none; d=google.com; s=arc-20160816; b=NhmIWsg05IpUh7VTDyBtCizt6A9wK0LCA0hfk9Fx4sEOfKq87lYVgsHZy1Lb67h7c8 8aKLOevVRn/2hK2GFP2QBQu828NtufVDFa1VdLFKBWGyPn7vOf1EuDN9e4Etngi9O2bW P2Wc9mOxqSP8WRxNNkiRyq0w5xmbusCYxydtnxFcURZQneQhIe22hVo6dnwfGvgOWitj w4HHrq/j+Ggr2PHoo24LksqmjTQRTIOrZ89Z44CN93nMnjFpb9ZWsBrixrKwZqicVOsH +VKP4r301F8DNG9/9x20Hy1xfrj78Iro+5kTdZr1SRRPnXe/3bvF4DKkM/GtQ8/thqDY l/KA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=B3w2Z4wKVmxtCQk+h+A9RHK7qypr3TYUJbVpvOqqCMU=; b=bzf5Oct6moOxTD4R+RpOn5eXy78hDKB5n8NFj2S0TUguzzobKGS4gAjWVKgMVPZqla QwxUlkHgjMT68Hc7JrYUTihrU8/eWAlC34NTEbf6r1g73cBOjWoW8aPsas3nRTtTXjkw 42TCvGKQh/c34Y61vNzhgr74myLCNxO3WJ9IaaSOhlihvNzXHO2iXxcM2yrqxy6EPuQ5 PI31nFhgpBh2Jbc/UNRcNdPWTjIbRD6YIrpaYOI/aYTu+Dlm6rgF73lLvU37psfrNblZ rzXcTBanbKXrJW+dOgfF8UdRyPWSL8ine6oezSl87HJrbO/8rZYhL+wzZyoKC9Y3Qpw3 pN/A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i10si487763edy.452.2021.03.22.09.36.14; Mon, 22 Mar 2021 09:36:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229547AbhCVQeR (ORCPT + 99 others); Mon, 22 Mar 2021 12:34:17 -0400 Received: from muru.com ([72.249.23.125]:45702 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230330AbhCVQdr (ORCPT ); Mon, 22 Mar 2021 12:33:47 -0400 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 47C59804C; Mon, 22 Mar 2021 16:34:39 +0000 (UTC) Date: Mon, 22 Mar 2021 18:33:40 +0200 From: Tony Lindgren To: Daniel Lezcano Cc: Thomas Gleixner , Keerthy , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tero Kristo Subject: Re: [PATCH 1/2] clocksource/drivers/timer-ti-dm: Prepare to handle dra7 timer wrap issue Message-ID: References: <20210304073737.15810-1-tony@atomide.com> <20210304073737.15810-2-tony@atomide.com> <556d55af-0b30-8751-6aef-2e1bb9db1a76@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <556d55af-0b30-8751-6aef-2e1bb9db1a76@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, * Daniel Lezcano [210322 15:56]: > On 04/03/2021 08:37, Tony Lindgren wrote: > > There is a timer wrap issue on dra7 for the ARM architected timer. > > In a typical clock configuration the timer fails to wrap after 388 days. > > > > To work around the issue, we need to use timer-ti-dm timers instead. > > > > Let's prepare for adding support for percpu timers by adding a common > > dmtimer_clkevt_init_common() and call it from dmtimer_clockevent_init(). > > This patch makes no intentional functional changes. > > > > Signed-off-by: Tony Lindgren > > --- > > [ ... ] > > > @@ -575,33 +574,60 @@ static int __init dmtimer_clockevent_init(struct device_node *np) > > */ > > writel_relaxed(OMAP_TIMER_CTRL_POSTED, t->base + t->ifctrl); > > > > + if (dev->cpumask == cpu_possible_mask) > > + irqflags = IRQF_TIMER; > > + else > > + irqflags = IRQF_TIMER | IRQF_NOBALANCING; > > Can you explain the reasoning behind the test above ? In the per cpu case we assign one dmtimer per cpu, and we want the interrupt handling on the assigned CPU. In the per cpu case we have the cpu specified with dev->cpumask unlike for the normal clockevent case. In the per cpu dmtimer case the interrupt line is not wired per cpu though, so I don't think we want to add IRQF_PERCPU here. Or do you have some better suggestion for the flags to use here? :) Regards, Tony