Received: by 2002:a05:6a10:9848:0:0:0:0 with SMTP id x8csp4133013pxf; Tue, 23 Mar 2021 03:37:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyQ+oq0l9YmbIjQlnW5aTo09vxwwXGCUvKhZLLoEpEcsRf24qVHA114bcOOfyCrZ3p/PzL9 X-Received: by 2002:aa7:c551:: with SMTP id s17mr3896712edr.291.1616495861844; Tue, 23 Mar 2021 03:37:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616495861; cv=none; d=google.com; s=arc-20160816; b=jkY1786pEM6UvVmy0c0PTL67slJnXk3RMqo0arWppHqGiMHPGPvFYQzGmPDNG4Uu5R Mg740INV1MmKp6Dmfd5avHCKDD7URu0qNxHNNRbc4UMv34R6YRlWyL+ASPpNguXdVp9I CrMCVWgFNqhKbQClK/AVsYOU0ICS4IRhxkRzMeyxchlVmQPlLr38aetFl6YztpRP8efM YiGS3oRLtIQwNyVlx6TG5FMC6VC14GWr/RrfoW2otHnSUP/uoaUdSg2TFUM4JtOJbG28 0rzrrBF8BNy+a3CX4zecCVeUXpRWfTQknoQlUTPNKEGXWzyGBfW6NbpQPljsNWblVzSY fV0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=8NQ3EUefRkKpGZLRv1upIVWlmSI/z4f7BTLhz2lGlrI=; b=BTCg6lZTqD7PN2koJiy8BjKWC3QaQ/FtD7a2XbYm26hMcYOXpDp2O+TxLhFT5aK5Mp WR+aplOknYl31ig8pLzZqSuGBwA66LmCYoBeNJEMo+LiONMUustP18oL8O8Hlb/d6683 i9pFyrSBT96SRct49yRuZ0Y9FRp47zJCCjCPrT4iNlmA0EBuquaSIgANQWhCKby01yIr /+ImW6CdWlvIOwkGNhZgC33ylVT/TuyNGxYKPwc2TkaZhpraTJAtLtBksJhrmg/uxtfl fGugB2DJthtK5dpysWHYNicJW9Hs81K1ENh/9YotQf5tIp2CQXmffRzZ6hSfTHYD3iw3 Hl/A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y14si12882960edw.480.2021.03.23.03.37.17; Tue, 23 Mar 2021 03:37:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230358AbhCWKfu (ORCPT + 99 others); Tue, 23 Mar 2021 06:35:50 -0400 Received: from foss.arm.com ([217.140.110.172]:43636 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229995AbhCWKfq (ORCPT ); Tue, 23 Mar 2021 06:35:46 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5FCF31042; Tue, 23 Mar 2021 03:35:46 -0700 (PDT) Received: from e123427-lin.arm.com (unknown [10.57.56.36]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 97A933F719; Tue, 23 Mar 2021 03:35:43 -0700 (PDT) From: Lorenzo Pieralisi To: Bjorn Helgaas , Rob Herring , Tom Joseph , Kishon Vijay Abraham I , Nadeem Athani Cc: Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lokesh Vutla , linux-omap@vger.kernel.org Subject: Re: [PATCH v4 0/4] AM64: Add PCIe bindings and driver support Date: Tue, 23 Mar 2021 10:35:33 +0000 Message-Id: <161649569906.24052.18351976498140721873.b4-ty@arm.com> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210308063550.6227-1-kishon@ti.com> References: <20210308063550.6227-1-kishon@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 8 Mar 2021 12:05:46 +0530, Kishon Vijay Abraham I wrote: > AM64 uses the same PCIe controller as in J7200, however AM642 EVM > doesn't have a clock generator (unlike J7200 base board). Here > the clock from the SERDES has to be routed to the PCIE connector. > This series provides an option for the pci-j721e.c driver to > drive reference clock output to the connector. > > v1 of the patch series can be found @ [1] > v2 of the patch series can be found @ [2] > v3 of the patch series can be found @ [3] > > [...] Applied to pci/cadence, thanks! [1/4] dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the connector https://git.kernel.org/lpieralisi/pci/c/f9875d1a36 [2/4] dt-bindings: PCI: ti,j721e: Add host mode dt-bindings for TI's AM64 SoC https://git.kernel.org/lpieralisi/pci/c/3201f355e9 [3/4] dt-bindings: PCI: ti,j721e: Add endpoint mode dt-bindings for TI's AM64 SoC https://git.kernel.org/lpieralisi/pci/c/6b7d5394c2 [4/4] PCI: j721e: Add support to provide refclk to PCIe connector https://git.kernel.org/lpieralisi/pci/c/49e0efdce7 Thanks, Lorenzo