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Date:   Tue, 23 Mar 2021 11:35:59 +0000
From:   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To:     Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
        Dilip Kota <eswara.kota@linux.intel.com>
Cc:     robh@kernel.org, linux-pci@vger.kernel.org, bhelgaas@google.com,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: dwc/intel-gw: Fix enabling the legacy PCI interrupt
 lines
Message-ID: <20210323113559.GE29286@e121166-lin.cambridge.arm.com>
References: <20210106135540.48420-1-martin.blumenstingl@googlemail.com>
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On Wed, Jan 06, 2021 at 02:55:40PM +0100, Martin Blumenstingl wrote:
> The legacy PCI interrupt lines need to be enabled using PCIE_APP_IRNEN
> bits 13 (INTA), 14 (INTB), 15 (INTC) and 16 (INTD). The old code however
> was taking (for example) "13" as raw value instead of taking BIT(13).
> Define the legacy PCI interrupt bits using the BIT() macro and then use
> these in PCIE_APP_IRN_INT.
> 
> Fixes: ed22aaaede44 ("PCI: dwc: intel: PCIe RC controller driver")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  drivers/pci/controller/dwc/pcie-intel-gw.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
> index 0cedd1f95f37..ae96bfbb6c83 100644
> --- a/drivers/pci/controller/dwc/pcie-intel-gw.c
> +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
> @@ -39,6 +39,10 @@
>  #define PCIE_APP_IRN_PM_TO_ACK		BIT(9)
>  #define PCIE_APP_IRN_LINK_AUTO_BW_STAT	BIT(11)
>  #define PCIE_APP_IRN_BW_MGT		BIT(12)
> +#define PCIE_APP_IRN_INTA		BIT(13)
> +#define PCIE_APP_IRN_INTB		BIT(14)
> +#define PCIE_APP_IRN_INTC		BIT(15)
> +#define PCIE_APP_IRN_INTD		BIT(16)
>  #define PCIE_APP_IRN_MSG_LTR		BIT(18)
>  #define PCIE_APP_IRN_SYS_ERR_RC		BIT(29)
>  #define PCIE_APP_INTX_OFST		12
> @@ -48,10 +52,8 @@
>  	PCIE_APP_IRN_RX_VDM_MSG | PCIE_APP_IRN_SYS_ERR_RC | \
>  	PCIE_APP_IRN_PM_TO_ACK | PCIE_APP_IRN_MSG_LTR | \
>  	PCIE_APP_IRN_BW_MGT | PCIE_APP_IRN_LINK_AUTO_BW_STAT | \
> -	(PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTA) | \
> -	(PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTB) | \
> -	(PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTC) | \
> -	(PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTD))
> +	PCIE_APP_IRN_INTA | PCIE_APP_IRN_INTB | \
> +	PCIE_APP_IRN_INTC | PCIE_APP_IRN_INTD)
>  
>  #define BUS_IATU_OFFSET			SZ_256M
>  #define RESET_INTERVAL_MS		100

This looks like a significant bug - which in turn raises the question
on how well this driver has been tested.

Dilip, can you review and ACK asap please ?

Thanks,
Lorenzo