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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR18MB1421.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: dc5ec07f-6838-4181-e121-08d8ee275c23 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Mar 2021 18:13:28.8526 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: RGPaBynbkrSwSkdEEgKQf58PjKVBEaIqnfcEQGiEvGbW0h4LgD6uapJ8NoKpNTnhFAIB13fqluM8lTYg1k4ahQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR18MB1343 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369,18.0.761 definitions=2021-03-23_09:2021-03-22,2021-03-23 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andrew , Please see inline, > -----Original Message----- > From: Andrew Lunn > Sent: Sunday, March 21, 2021 7:45 PM > To: Hariprasad Kelam > Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org; kuba@kernel.org= ; > davem@davemloft.net; Sunil Kovvuri Goutham ; > Linu Cherian ; Geethasowjanya Akula > ; Jerin Jacob Kollanukkaran ; > Subbaraya Sundeep Bhatta > Subject: [EXT] Re: [net-next PATCH 0/8] configuration support for switch > headers & phy >=20 > On Sun, Mar 21, 2021 at 05:39:50PM +0530, Hariprasad Kelam wrote: > > This series of patches add support for parsing switch headers and > > configuration support for phy modulation type(NRZ or PAM4). > > > > PHYs that support changing modulation type ,user can configure it > > through private flags pam4. > > > > Marvell switches support DSA(distributed switch architecture) with > > different switch headers like FDSA and EDSA. This patch series adds > > private flags to enable user to configure interface in fdsa/edsa mode > > such that flow steering (forwading packets to pf/vf depending on > > switch header fields) and packet parsing can be acheived. >=20 > Hi Hariprasad >=20 > Private flags sound very wrong here. I would expect to see some integrati= on > between the switchdev/DSA driver and the MAC driver. > Please show how this works in combination with drivers/net/dsa/mv88e6xxx > or drivers/net/ethernet/marvell/prestera. >=20 Octeontx2 silicon supports NPC (network parser and cam) unit , through whi= ch packet parsing and packet classification is achieved. Packet parsing extracting different fields from each layer. DMAC + SMAC --> LA VLAN ID --> LB SIP + DIP --> LC TCP SPORT + DPO= RT --> LD And packet classification is achieved through flow identification in k= ey extraction and mcam search key . User can install mcam rules With action as =20 forward packet to PF and to receive queue 0 forward packet to VF and with as RSS ( Receive side scaling) drop the packet=20 etc.. Now with switch header ( EDSA /FDSA) and HIGIG2 appended to regular pack= et , NPC can not parse these Ingress packets as these headers does not have fixed headers. To achieve= this Special PKIND( port kind) is allocated in hardware which will help NPC to parse the packets. For example incase of EDSA 8 byte header which is placed right after SMAC = , special PKIND reserved for EDSA helps NPC to=20 Identify the input packet is EDSA . Such that NPC can extract fields in t= his header and forward to=20 Parse rest of the headers. Same is the case with higig2 header where 16 bytes header is placed at sta= rt of the packet. In this case private flags helps user to configure interface in EDSA/FDSA o= r HIGIG2. Such that special PKIND reserved for that header are assigned to the interface. The scope of= the patch series is how User can configure interface mode as switch header(HIGIG2/EDSA etc) .In our= case no DSA logical Ports are created as these headers can be stripped by NPC. Thanks, Hariprasad k =20 > Andrew