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[23.128.96.18]) by mx.google.com with ESMTP id l14si1917752eji.711.2021.03.24.07.50.11; Wed, 24 Mar 2021 07:50:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236247AbhCXOqS (ORCPT + 99 others); Wed, 24 Mar 2021 10:46:18 -0400 Received: from mail.kernel.org ([198.145.29.99]:42096 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236294AbhCXOqA (ORCPT ); Wed, 24 Mar 2021 10:46:00 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 12A87619F3; Wed, 24 Mar 2021 14:46:00 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lP4lh-003XaC-No; Wed, 24 Mar 2021 14:45:58 +0000 Date: Wed, 24 Mar 2021 14:45:56 +0000 Message-ID: <874kh0k3tn.wl-maz@kernel.org> From: Marc Zyngier To: Bharat Kumar Gogada Cc: "lorenzo.pieralisi@arm.com" , Bjorn Helgaas , Frank Wunderlich , Thierry Reding , Thomas Gleixner , Rob Herring , Will Deacon , "K. Y. Srinivasan" , Haiyang Zhang , Stephen Hemminger , Michael Kelley , Wei Liu , Thierry Reding , Jonathan Hunter , Ryder Lee , Marek Vasut , Yoshihiro Shimoda , Michal Simek , Paul Walmsley , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-hyperv@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "linux-mediatek@lists.infradead.org" , "linux-renesas-soc@vger.kernel.org" , "kernel-team@android.com" Subject: Re: [PATCH v2 05/15] PCI: xilinx: Convert to MSI domains In-Reply-To: References: <20210322184614.802565-1-maz@kernel.org> <20210322184614.802565-6-maz@kernel.org> <877dlwk805.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: bharatku@xilinx.com, lorenzo.pieralisi@arm.com, bhelgaas@google.com, frank-w@public-files.de, treding@nvidia.com, tglx@linutronix.de, robh@kernel.org, will@kernel.org, kys@microsoft.com, haiyangz@microsoft.com, sthemmin@microsoft.com, mikelley@microsoft.com, wei.liu@kernel.org, thierry.reding@gmail.com, jonathanh@nvidia.com, ryder.lee@mediatek.com, marek.vasut+renesas@gmail.com, yoshihiro.shimoda.uh@renesas.com, michals@xilinx.com, paul.walmsley@sifive.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hyperv@vger.kernel.org, linux-tegra@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 24 Mar 2021 13:56:16 +0000, Bharat Kumar Gogada wrote: > > Thanks for that. Can you please try the following patch and let me know if it > > helps? > > > > Thanks, > > > > M. > > > > diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/pcie- > > xilinx.c > > index ad9abf405167..14001febf59a 100644 > > --- a/drivers/pci/controller/pcie-xilinx.c > > +++ b/drivers/pci/controller/pcie-xilinx.c > > @@ -194,8 +194,18 @@ static struct pci_ops xilinx_pcie_ops = { > > > > /* MSI functions */ > > > > +static void xilinx_msi_top_irq_ack(struct irq_data *d) { > > + /* > > + * xilinx_pcie_intr_handler() will have performed the Ack. > > + * Eventually, this should be fixed and the Ack be moved in > > + * the respective callbacks for INTx and MSI. > > + */ > > +} > > + > > static struct irq_chip xilinx_msi_top_chip = { > > .name = "PCIe MSI", > > + .irq_ack = xilinx_msi_top_irq_ack, > > }; > > > > static int xilinx_msi_set_affinity(struct irq_data *d, const struct cpumask > > *mask, bool force) @@ -206,7 +216,7 @@ static int > > xilinx_msi_set_affinity(struct irq_data *d, const struct cpumask *mas static > > void xilinx_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { > > struct xilinx_pcie_port *pcie = irq_data_get_irq_chip_data(data); > > - phys_addr_t pa = virt_to_phys(pcie); > > + phys_addr_t pa = ALIGN_DOWN(virt_to_phys(pcie), SZ_4K); > > > > msg->address_lo = lower_32_bits(pa); > > msg->address_hi = upper_32_bits(pa); > > @@ -468,7 +478,7 @@ static int xilinx_pcie_init_irq_domain(struct > > xilinx_pcie_port *port) > > > > /* Setup MSI */ > > if (IS_ENABLED(CONFIG_PCI_MSI)) { > > - phys_addr_t pa = virt_to_phys(port); > > + phys_addr_t pa = ALIGN_DOWN(virt_to_phys(port), SZ_4K); > > > > ret = xilinx_allocate_msi_domains(port); > > if (ret) > > > Thanks Marc. > With above patch now everything works fine, tested a Samsung NVMe SSD. > tst~# lspci > 00:00.0 PCI bridge: Xilinx Corporation Device 0706 > 01:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller 172Xa/172Xb (rev 01) Great, thanks for giving it a shot. Can I take this as a Tested-by: tag? Thanks, M. -- Without deviation from the norm, progress is not possible.