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[23.128.96.18]) by mx.google.com with ESMTP id v5si3811517edc.166.2021.03.25.01.59.01; Thu, 25 Mar 2021 01:59:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s+p8JtdX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229533AbhCYI5t (ORCPT + 99 others); Thu, 25 Mar 2021 04:57:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229622AbhCYI5h (ORCPT ); Thu, 25 Mar 2021 04:57:37 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAAD3C061760 for ; Thu, 25 Mar 2021 01:57:36 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id f26so2116873ljp.8 for ; Thu, 25 Mar 2021 01:57:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=IBw+fqPCYGPDI6K3X71IFi8mM+m8z83H8t7eBrf5JCU=; b=s+p8JtdX7JNqKg148kB7YqJ2LzP3jEieZthb9Fn07U2hVcxHFIwZhmrymmZ6B2A9tu /nk0P6Ce6W+5pUUowM1vDBrKHCcAWTa4EGvPT0/jpjwRNTp17F/RiNN2GJrP9fRVWFVG tYGH+7g30olnPq4l+uqKbW5PpvNY5hNIznMvAkW9r2kx5DbU2nEFdRpViMX3K1951+N9 Ks0WkFhnneCcIthTxwRZ4UwQyxfbd9KHNyL+r3U4iSo9xR2qgRPWlbqr0mfcW8nmUUjK WJnyoDtm580Tg08lC4znFUQUhZKycbQj5Dw1Tdd84SFLdchTyMRwToZWyUFKyjIsLIwg gTPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=IBw+fqPCYGPDI6K3X71IFi8mM+m8z83H8t7eBrf5JCU=; b=D8I06IPmRndP+TTpuVBmbQ5nWOmDIN+PDMrti2SgP1iOyx1vOgpvbuu4gsjPJ9aZ1f W9A7xYusFWg9uUpfYmu6hRT4hRwRopGidUMM/QM89SZaVlvwZFW8K68HygUkDCKSVKH2 UuhzIvrfolff9mYb8cwyGO0NhpFPn/aMDRJSpC28tT2MNBHZht8AfzKTdDe93xS3YD8D /hEXk4hf+wkB/p+ZZAmwKmdjPO+nosYsAHIE9vTcQDJ4+lRYTbQZDsEAQyMWAwfwwg8O 8wU80Idt9ibdV5lrrJrFLv8752fXL9fYe4vJTvrkRfIt3fOehAsu1c0pLqmhOMYfC6mh 1tmQ== X-Gm-Message-State: AOAM531iz66V6/pIbVNbr6RXrDDFhQHbrre/cNCKdKN+RfiX08AfX01O rciFNkXYnohUPqmPUa/iidJRx2eTsdDU0RsPOTZVGw== X-Received: by 2002:a2e:700a:: with SMTP id l10mr4951839ljc.368.1616662655294; Thu, 25 Mar 2021 01:57:35 -0700 (PDT) MIME-Version: 1.0 References: <1615969516-87663-1-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com> <1615969516-87663-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com> In-Reply-To: From: Linus Walleij Date: Thu, 25 Mar 2021 09:57:23 +0100 Message-ID: Subject: Re: [PATCH v4 3/3] pinctrl: Add Xilinx ZynqMP pinctrl driver support To: Sai Krishna Potthuri Cc: Andy Shevchenko , Rob Herring , Michal Simek , Greg Kroah-Hartman , linux-arm Mailing List , Linux Kernel Mailing List , devicetree , "open list:GPIO SUBSYSTEM" , git , "saikrishna12468@gmail.com" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 22, 2021 at 4:25 PM Sai Krishna Potthuri wrote: > [Andy] > > > > > + PIN_CONFIG_IOSTANDARD = PIN_CONFIG_END + 1, }; > > > > > > > > I'm lost here. What is IO standard exactly? Why it can't be in > > > > generic headers? > > > It represents LVCMOS 3.3 volts/ LVCMOS 1.8 volts. > > > Since this is specific to Xilinx ZynqMP platform, considered to be > > > added in the driver file. > > > > So, why can't we create a couple of bits to represent this voltages in the > > generic header and gain usability for others as well? > > I see some drivers are maintaining the configuration list in the driver file, if > the configuration is specific to the driver. > > We can move this to generic header if it is used by others as well. > Ok, will wait for Linus to comment. > > > > Linus? While it is fine to add custom pin config options to pin controllers for hopelessly idiomatic stuff, this does look like it should be using PIN_CONFIG_POWER_SOURCE with the voltage rail as parameter, see include/linux/pinctrl/pinconf-generic.h If you're not using that then tell us why. Yours, Linus Walleij