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Date:   Thu, 25 Mar 2021 15:49:48 +0100
From:   Thierry Reding <thierry.reding@gmail.com>
To:     Dmitry Osipenko <digetx@gmail.com>
Cc:     Rob Herring <robh@kernel.org>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        Mark Brown <broonie@kernel.org>,
        Paul Fertser <fercerpav@gmail.com>,
        Matt Merhar <mattmerhar@protonmail.com>,
        Peter Geis <pgwipeout@gmail.com>,
        Nicolas Chauvet <kwizart@gmail.com>,
        Viresh Kumar <vireshk@kernel.org>,
        Stephen Boyd <sboyd@kernel.org>,
        =?utf-8?B?TWljaGHFgiBNaXJvc8WCYXc=?= <mirq-linux@rere.qmqm.pl>,
        Krzysztof Kozlowski <krzk@kernel.org>,
        devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 3/6] dt-bindings: power: tegra: Add binding for core
 power domain
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References: <20210314164810.26317-1-digetx@gmail.com>
 <20210314164810.26317-4-digetx@gmail.com>
 <20210323224826.GA1490612@robh.at.kernel.org>
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On Wed, Mar 24, 2021 at 02:01:29AM +0300, Dmitry Osipenko wrote:
> 24.03.2021 01:48, Rob Herring =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
> > On Sun, Mar 14, 2021 at 07:48:07PM +0300, Dmitry Osipenko wrote:
> >> All NVIDIA Tegra SoCs have a core power domain where majority of hardw=
are
> >> blocks reside. Add binding for the core power domain.
> >>
> >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> >> ---
> >>  .../power/nvidia,tegra20-core-domain.yaml     | 51 +++++++++++++++++++
> >>  1 file changed, 51 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/power/nvidia,teg=
ra20-core-domain.yaml
> >>
> >> diff --git a/Documentation/devicetree/bindings/power/nvidia,tegra20-co=
re-domain.yaml b/Documentation/devicetree/bindings/power/nvidia,tegra20-cor=
e-domain.yaml
> >> new file mode 100644
> >> index 000000000000..4692489d780a
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/power/nvidia,tegra20-core-doma=
in.yaml
> >> @@ -0,0 +1,51 @@
> >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/power/nvidia,tegra20-core-domain.y=
aml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: NVIDIA Tegra Core Power Domain
> >> +
> >> +maintainers:
> >> +  - Dmitry Osipenko <digetx@gmail.com>
> >> +  - Jon Hunter <jonathanh@nvidia.com>
> >> +  - Thierry Reding <thierry.reding@gmail.com>
> >> +
> >> +allOf:
> >> +  - $ref: power-domain.yaml#
> >> +
> >> +properties:
> >> +  compatible:
> >> +    enum:
> >> +      - nvidia,tegra20-core-domain
> >> +      - nvidia,tegra30-core-domain
> >> +
> >> +  operating-points-v2:
> >> +    description:
> >> +      Should contain level, voltages and opp-supported-hw property.
> >> +      The supported-hw is a bitfield indicating SoC speedo or process
> >> +      ID mask.
> >> +
> >> +  "#power-domain-cells":
> >> +    const: 0
> >> +
> >> +  power-supply:
> >> +    description:
> >> +      Phandle to voltage regulator connected to the SoC Core power ra=
il.
> >> +
> >> +required:
> >> +  - compatible
> >> +  - operating-points-v2
> >> +  - "#power-domain-cells"
> >> +  - power-supply
> >> +
> >> +additionalProperties: false
> >> +
> >> +examples:
> >> +  - |
> >> +    power-domain {
> >> +        compatible =3D "nvidia,tegra20-core-domain";
> >> +        operating-points-v2 =3D <&opp_table>;
> >> +        power-supply =3D <&regulator>;
> >> +        #power-domain-cells =3D <0>;
> >=20
> > AFAICT, there's no way to access this 'hardware'?
> correct

To avoid exposing this "virtual" device in device tree, could this
instead be modelled as a child node of the PMC node? We already expose a
couple of generic power domains that way on Tegra210 and later, so
perhaps some of that infrastructure can be reused? I suppose given that
this is different from the standard powergate domains that we expose so
far, this may need a different implementation, but from a device tree
bindings point of view it could fit in with that.

Thierry

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