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[23.128.96.18]) by mx.google.com with ESMTP id s18si4963767ejj.88.2021.03.25.11.46.09; Thu, 25 Mar 2021 11:46:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=fail (test mode) header.i=@shipmail.org header.s=mail header.b=Wj1JOJcd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230104AbhCYSmf (ORCPT + 99 others); Thu, 25 Mar 2021 14:42:35 -0400 Received: from ste-pvt-msa1.bahnhof.se ([213.80.101.70]:22383 "EHLO ste-pvt-msa1.bahnhof.se" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230085AbhCYSmU (ORCPT ); Thu, 25 Mar 2021 14:42:20 -0400 Received: from localhost (localhost [127.0.0.1]) by ste-pvt-msa1.bahnhof.se (Postfix) with ESMTP id 435E03F3B2; Thu, 25 Mar 2021 19:42:19 +0100 (CET) Authentication-Results: ste-pvt-msa1.bahnhof.se; dkim=pass (1024-bit key; unprotected) header.d=shipmail.org header.i=@shipmail.org header.b=Wj1JOJcd; dkim-atps=neutral X-Virus-Scanned: Debian amavisd-new at bahnhof.se X-Spam-Flag: NO X-Spam-Score: -2.1 X-Spam-Level: X-Spam-Status: No, score=-2.1 tagged_above=-999 required=6.31 tests=[BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, URIBL_BLOCKED=0.001] autolearn=ham autolearn_force=no Received: from ste-pvt-msa1.bahnhof.se ([127.0.0.1]) by localhost (ste-pvt-msa1.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MF524rY7BNQG; Thu, 25 Mar 2021 19:42:18 +0100 (CET) Received: by ste-pvt-msa1.bahnhof.se (Postfix) with ESMTPA id 4DA9D3F27F; Thu, 25 Mar 2021 19:42:17 +0100 (CET) Received: from [10.249.254.165] (unknown [192.198.151.44]) by mail1.shipmail.org (Postfix) with ESMTPSA id E75B436059E; Thu, 25 Mar 2021 19:42:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=shipmail.org; s=mail; t=1616697736; bh=8GFYWnQPYCiN2M+PBNjHsNO3soivwm3ln02svNRajX8=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=Wj1JOJcdbTP/JTvFBvpvJy9mle9Q6w++mH7KUmgFoeLdDz0gEgltJCQEOYtHkHlQw oGzJznK3W4yJK20Ft0Qqqa2v52HBleZr7q2Ikla8PDvw9pgO/my42DJuvmzxnOVfLq iz7nc9TafMwV7HJONjvuCiUULNZFa0+d3ethgJo8= Subject: Re: [RFC PATCH 1/2] mm,drm/ttm: Block fast GUP to TTM huge pages To: Jason Gunthorpe Cc: Dave Hansen , "Williams, Dan J" , "dri-devel@lists.freedesktop.org" , "christian.koenig@amd.com" , "airlied@linux.ie" , "linux-mm@kvack.org" , "linux-kernel@vger.kernel.org" , "akpm@linux-foundation.org" References: <75423f64-adef-a2c4-8e7d-2cb814127b18@intel.com> <6b0de827-738d-b3c5-fc79-8ca9047bad35@intel.com> <9f789d64-940f-c728-8d5e-aab74d562fb6@shipmail.org> <20210325175504.GH2356281@nvidia.com> <1ed48d99-1cd9-d87b-41dd-4169afc77f70@shipmail.org> <20210325182442.GI2356281@nvidia.com> From: =?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?= Message-ID: <6c952be3-8be8-c4c9-a1f9-ddec027645bf@shipmail.org> Date: Thu, 25 Mar 2021 19:42:13 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210325182442.GI2356281@nvidia.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/25/21 7:24 PM, Jason Gunthorpe wrote: > On Thu, Mar 25, 2021 at 07:13:33PM +0100, Thomas Hellström (Intel) wrote: >> On 3/25/21 6:55 PM, Jason Gunthorpe wrote: >>> On Thu, Mar 25, 2021 at 06:51:26PM +0100, Thomas Hellström (Intel) wrote: >>>> On 3/24/21 9:25 PM, Dave Hansen wrote: >>>>> On 3/24/21 1:22 PM, Thomas Hellström (Intel) wrote: >>>>>>> We also have not been careful at *all* about how _PAGE_BIT_SOFTW* are >>>>>>> used.  It's quite possible we can encode another use even in the >>>>>>> existing bits. >>>>>>> >>>>>>> Personally, I'd just try: >>>>>>> >>>>>>> #define _PAGE_BIT_SOFTW5        57      /* available for programmer */ >>>>>>> >>>>>> OK, I'll follow your advise here. FWIW I grepped for SW1 and it seems >>>>>> used in a selftest, but only for PTEs AFAICT. >>>>>> >>>>>> Oh, and we don't care about 32-bit much anymore? >>>>> On x86, we have 64-bit PTEs when running 32-bit kernels if PAE is >>>>> enabled. IOW, we can handle the majority of 32-bit CPUs out there. >>>>> >>>>> But, yeah, we don't care about 32-bit. :) >>>> Hmm, >>>> >>>> Actually it makes some sense to use SW1, to make it end up in the same dword >>>> as the PSE bit, as from what I can tell, reading of a 64-bit pmd_t on 32-bit >>>> PAE is not atomic, so in theory a huge pmd could be modified while reading >>>> the pmd_t making the dwords inconsistent.... How does that work with fast >>>> gup anyway? >>> It loops to get an atomic 64 bit value if the arch can't provide an >>> atomic 64 bit load >> Hmm, ok, I see a READ_ONCE() in gup_pmd_range(), and then the resulting pmd >> is dereferenced either in try_grab_compound_head() or __gup_device_huge(), >> before the pmd is compared to the value the pointer is currently pointing >> to. Couldn't those dereferences be on invalid pointers? > Uhhhhh.. That does look questionable, yes. Unless there is some tricky > reason why a 64 bit pmd entry on a 32 bit arch either can't exist or > has a stable upper 32 bits.. > > The pte does it with ptep_get_lockless(), we probably need the same > for the other levels too instead of open coding a READ_ONCE? > > Jason Yes, unless that comment before local_irq_disable() means some magic is done to prevent bad things happening, but I guess if it's needed for ptes, it's probably needed for pmds and puds as well. /Thomas