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References: <20210326091547.12375-1-zhangqing@rock-chips.com> <20210326091547.12375-4-zhangqing@rock-chips.com>
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From:   Enric Balletbo Serra <eballetbo@gmail.com>
Date:   Fri, 26 Mar 2021 10:40:46 +0100
Message-ID: <CAFqH_503DyLAd5XUxdTiZrDbdTRFt=rjoQy5-bSH-4DiKrdd8w@mail.gmail.com>
Subject: Re: [PATCH v5 03/11] arm: dts: rockchip: Fix power-controller node
 names for rk3288
To:     Elaine Zhang <zhangqing@rock-chips.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        =?UTF-8?Q?Heiko_St=C3=BCbner?= <heiko@sntech.de>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>,
        linux-kernel <linux-kernel@vger.kernel.org>, cl@rock-chips.com,
        huangtao@rock-chips.com, kever.yang@rock-chips.com,
        tony.xie@rock-chips.com, finley.xiao@rock-chips.com
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Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de
mar=C3=A7 2021 a les 10:16:
>
> Use more generic names (as recommended in the device tree specification
> or the binding documentation)
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>

> ---
>  arch/arm/boot/dts/rk3288.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dts=
i
> index ea7416c31f9b..6f4d7929e351 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -769,7 +769,7 @@
>                          *      *_HDMI          HDMI
>                          *      *_MIPI_*        MIPI
>                          */
> -                       pd_vio@RK3288_PD_VIO {
> +                       power-domain@RK3288_PD_VIO {
>                                 reg =3D <RK3288_PD_VIO>;
>                                 clocks =3D <&cru ACLK_IEP>,
>                                          <&cru ACLK_ISP>,
> @@ -811,7 +811,7 @@
>                          * Note: The following 3 are HEVC(H.265) clocks,
>                          * and on the ACLK_HEVC_NIU (NOC).
>                          */
> -                       pd_hevc@RK3288_PD_HEVC {
> +                       power-domain@RK3288_PD_HEVC {
>                                 reg =3D <RK3288_PD_HEVC>;
>                                 clocks =3D <&cru ACLK_HEVC>,
>                                          <&cru SCLK_HEVC_CABAC>,
> @@ -825,7 +825,7 @@
>                          * (video endecoder & decoder) clocks that on the
>                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
>                          */
> -                       pd_video@RK3288_PD_VIDEO {
> +                       power-domain@RK3288_PD_VIDEO {
>                                 reg =3D <RK3288_PD_VIDEO>;
>                                 clocks =3D <&cru ACLK_VCODEC>,
>                                          <&cru HCLK_VCODEC>;
> @@ -836,7 +836,7 @@
>                          * Note: ACLK_GPU is the GPU clock,
>                          * and on the ACLK_GPU_NIU (NOC).
>                          */
> -                       pd_gpu@RK3288_PD_GPU {
> +                       power-domain@RK3288_PD_GPU {
>                                 reg =3D <RK3288_PD_GPU>;
>                                 clocks =3D <&cru ACLK_GPU>;
>                                 pm_qos =3D <&qos_gpu_r>,
> --
> 2.17.1
>
>
>
>
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