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From:   Enric Balletbo Serra <eballetbo@gmail.com>
Date:   Fri, 26 Mar 2021 10:52:48 +0100
Message-ID: <CAFqH_53qnWdRQ01kRxVAKRWZnimW+gyNO=pv+ET4xFQB5QGOtA@mail.gmail.com>
Subject: Re: [PATCH v5 08/11] dt-bindings: add power-domain header for RK3568 SoCs
To:     Elaine Zhang <zhangqing@rock-chips.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        =?UTF-8?Q?Heiko_St=C3=BCbner?= <heiko@sntech.de>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>,
        linux-kernel <linux-kernel@vger.kernel.org>, cl@rock-chips.com,
        huangtao@rock-chips.com, kever.yang@rock-chips.com,
        tony.xie@rock-chips.com, finley.xiao@rock-chips.com
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Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de
mar=C3=A7 2021 a les 10:18:
>
> According to a description from TRM, add all the power domains
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>

> ---
>  include/dt-bindings/power/rk3568-power.h | 32 ++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
>  create mode 100644 include/dt-bindings/power/rk3568-power.h
>
> diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindin=
gs/power/rk3568-power.h
> new file mode 100644
> index 000000000000..6cc1af1a9d26
> --- /dev/null
> +++ b/include/dt-bindings/power/rk3568-power.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__
> +#define __DT_BINDINGS_POWER_RK3568_POWER_H__
> +
> +/* VD_CORE */
> +#define RK3568_PD_CPU_0                0
> +#define RK3568_PD_CPU_1                1
> +#define RK3568_PD_CPU_2                2
> +#define RK3568_PD_CPU_3                3
> +#define RK3568_PD_CORE_ALIVE   4
> +
> +/* VD_PMU */
> +#define RK3568_PD_PMU          5
> +
> +/* VD_NPU */
> +#define RK3568_PD_NPU          6
> +
> +/* VD_GPU */
> +#define RK3568_PD_GPU          7
> +
> +/* VD_LOGIC */
> +#define RK3568_PD_VI           8
> +#define RK3568_PD_VO           9
> +#define RK3568_PD_RGA          10
> +#define RK3568_PD_VPU          11
> +#define RK3568_PD_CENTER       12
> +#define RK3568_PD_RKVDEC       13
> +#define RK3568_PD_RKVENC       14
> +#define RK3568_PD_PIPE         15
> +#define RK3568_PD_LOGIC_ALIVE  16
> +
> +#endif
> --
> 2.17.1
>
>
>
>
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