Received: by 2002:a05:6a10:9848:0:0:0:0 with SMTP id x8csp1598056pxf; Fri, 26 Mar 2021 10:30:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyjAAeb/4EZSDMoFaVXlo2wAkZRZzNcSdUB30jm8NN/aGJbGNDTSJPmcRL8pnGo4rc4Onpy X-Received: by 2002:a17:906:c9c2:: with SMTP id hk2mr16652965ejb.244.1616779813569; Fri, 26 Mar 2021 10:30:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616779813; cv=none; d=google.com; s=arc-20160816; b=AgdWAKIyVEUh88CLhg7QXi1CEYKTHDE1Cb/2Czi8sUVgHMtD+qK6gzuGQRPwv1SULd 9FDTpSREk9xIRFPOIleCM8/cAIifNLxqwlhzSUOKe/5/x7CB4QeasSJroH51x5QfOK0+ 1KRfJmRnXWSbudahYd9kDf6C/lzM4qDYgV01yWtxYsVZHCrlqrDSZBzWe8BiiIbEDMb2 FjTWuuvo29sr+19kGIGM1vjBYJspHzNDyb7tnZ9ezrDEwNhM5zyJzKFaLzzM6qygK7fg 3H4gMsFalNE6vO4uUQ7hzZsy3mFaX+N/JAIBhlel6oixLoljN5g++6+mXoVnrw+fz8u7 j7pQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=1JrvGVjvnU4OleZHvZNBHn3IUwN+tQcLM7GpfSmRkZk=; b=UofJvoZd2NSaSckgnQ0I3eamZ+iCbxZrqNisIAmerdt2J/Qe3HnF0DA3k8p44Ye9or yY4G1nGkGETWckasG31Hu06iuIKWzz6e86rg29Z96XQi/dSUnLYc1bB6ZPFv1L7P/p7M KiuVXzkH7T3l2ZcEpDhapwqrEk07+aWghRVdtqPmuLuAhIwNVrZr81ZebnDjRigns6Zd ip/FcofOHtvgLDJhrrQuyhzY1r9RxwsaxXtAz4kPBy0cRTXEKqDC7W/+mUUxTPXzsyC7 1k7sFEJ3muL4dOuZZrX1cvrIGC5Dsko9VQp10ecOWHvacfzFoo2MbImzi7IW0Q3w0V6g U+RQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=cwpkHyQr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id o6si2224644ejg.157.2021.03.26.10.29.51; Fri, 26 Mar 2021 10:30:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=cwpkHyQr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230248AbhCZR1u (ORCPT + 99 others); Fri, 26 Mar 2021 13:27:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230224AbhCZR1p (ORCPT ); Fri, 26 Mar 2021 13:27:45 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58B28C0613B1 for ; Fri, 26 Mar 2021 10:27:45 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id u5so9568611ejn.8 for ; Fri, 26 Mar 2021 10:27:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=1JrvGVjvnU4OleZHvZNBHn3IUwN+tQcLM7GpfSmRkZk=; b=cwpkHyQrULLTxS7hyIyPePeFi/FNtWZ3wrU8DFAd6e74G1o94qmH7Z5PjWR8yr5z1r sgpyKyCURNT2pAZYYtT4o1xIv830XPuXSi07uQQ+jqPykxJW/tfNNu1GDRVqbAXCl4Hz nBRpS61VfXySqkW2Bx1fZJC4qhxNH9f04jCpVCDUd1Brf9Ko4JlEUr1S5u+1WhMo9n/Z GkzwtQ0CYVWe4DfIsGLtfv6b+/ocnK8JELWYGPm57NUUs4U0GaouCUQWF/T81DrMcXuq Z6tLBq2cU/VsK4UcPMjLnxwxXN++4BJ+LINlfni/VXPu6o1YOZnpxfeGHVfUjnDUYY1l hhRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=1JrvGVjvnU4OleZHvZNBHn3IUwN+tQcLM7GpfSmRkZk=; b=rC2PTeJWpGf9GM8vsDWIaP7TIASoEa9kAX0GP1IRrIkuwMmJPlcqHEZQpKnGFZDZfp sU+A0TVfREG3GJy0bUBhB8Hxc+yPLU5mQTrl4hK8h95XAQSyvOZeQ53rIP9lI20uhL2t 0QRIcGghGtoLIVvzG6E28+rIA8acLAcEG8DoT7U7TNIgNq4uoLw7B2eZBSeIBRYJCOKK AZh1GJAJbQF9jR/EKQcCa+TTzld60/teFuRue36Sju8n51kvrbsvF4gwfPIX6D/9g2NV 78SGbWAswNYdORCUKbWDSZixTpqqJJ1U9IGcInrXtKjhMWlUWEXyWzY4JjnSl6eNRzPc hP1g== X-Gm-Message-State: AOAM530MKC7tZRFDeMER2XcEtqwemQXgF5Mpka3Z/kFfTuf6cGngwixg 0ZMcZJzC0UGFEd8cAOhCy2zYxDav72uDRjOnvH2Iow== X-Received: by 2002:a17:906:c0c8:: with SMTP id bn8mr16475296ejb.445.1616779663961; Fri, 26 Mar 2021 10:27:43 -0700 (PDT) MIME-Version: 1.0 References: <4c259d34b5943bf384fd3cb0d98eccf798a34f0f.1615038553.git.syednwaris@gmail.com> <36db7be3-73b6-c822-02e8-13e3864b0463@xilinx.com> In-Reply-To: <36db7be3-73b6-c822-02e8-13e3864b0463@xilinx.com> From: Bartosz Golaszewski Date: Fri, 26 Mar 2021 18:27:33 +0100 Message-ID: Subject: Re: [PATCH v3 3/3] gpio: xilinx: Utilize generic bitmap_get_value and _set_value To: Michal Simek Cc: Syed Nayyar Waris , Srinivas Neeli , Andy Shevchenko , William Breathitt Gray , Arnd Bergmann , Robert Richter , Linus Walleij , Masahiro Yamada , Andrew Morton , Zhang Rui , Daniel Lezcano , Amit Kucheria , Linux-Arch , linux-gpio , LKML , arm-soc , linux-pm , Srinivas Goud Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 8, 2021 at 8:13 AM Michal Simek wrote: > > > > On 3/6/21 3:06 PM, Syed Nayyar Waris wrote: > > This patch reimplements the xgpio_set_multiple() function in > > drivers/gpio/gpio-xilinx.c to use the new generic functions: > > bitmap_get_value() and bitmap_set_value(). The code is now simpler > > to read and understand. Moreover, instead of looping for each bit > > in xgpio_set_multiple() function, now we can check each channel at > > a time and save cycles. > > > > Cc: Bartosz Golaszewski > > Cc: Michal Simek > > Signed-off-by: Syed Nayyar Waris > > Acked-by: William Breathitt Gray > > --- > > drivers/gpio/gpio-xilinx.c | 63 +++++++++++++++++++------------------- > > 1 file changed, 32 insertions(+), 31 deletions(-) > > > > diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c > > index be539381fd82..8445e69cf37b 100644 > > --- a/drivers/gpio/gpio-xilinx.c > > +++ b/drivers/gpio/gpio-xilinx.c > > @@ -15,6 +15,7 @@ > > #include > > #include > > #include > > +#include "gpiolib.h" > > > > /* Register Offset Definitions */ > > #define XGPIO_DATA_OFFSET (0x0) /* Data register */ > > @@ -141,37 +142,37 @@ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, > > { > > unsigned long flags; > > struct xgpio_instance *chip = gpiochip_get_data(gc); > > - int index = xgpio_index(chip, 0); > > - int offset, i; > > - > > - spin_lock_irqsave(&chip->gpio_lock[index], flags); > > - > > - /* Write to GPIO signals */ > > - for (i = 0; i < gc->ngpio; i++) { > > - if (*mask == 0) > > - break; > > - /* Once finished with an index write it out to the register */ > > - if (index != xgpio_index(chip, i)) { > > - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + > > - index * XGPIO_CHANNEL_OFFSET, > > - chip->gpio_state[index]); > > - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); > > - index = xgpio_index(chip, i); > > - spin_lock_irqsave(&chip->gpio_lock[index], flags); > > - } > > - if (__test_and_clear_bit(i, mask)) { > > - offset = xgpio_offset(chip, i); > > - if (test_bit(i, bits)) > > - chip->gpio_state[index] |= BIT(offset); > > - else > > - chip->gpio_state[index] &= ~BIT(offset); > > - } > > - } > > - > > - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + > > - index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); > > - > > - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); > > + u32 *const state = chip->gpio_state; > > + unsigned int *const width = chip->gpio_width; > > + > > + DECLARE_BITMAP(old, 64); > > + DECLARE_BITMAP(new, 64); > > + DECLARE_BITMAP(changed, 64); > > + > > + spin_lock_irqsave(&chip->gpio_lock[0], flags); > > + spin_lock(&chip->gpio_lock[1]); > > + > > + bitmap_set_value(old, 64, state[0], width[0], 0); > > + bitmap_set_value(old, 64, state[1], width[1], width[0]); > > + bitmap_replace(new, old, bits, mask, gc->ngpio); > > + > > + bitmap_set_value(old, 64, state[0], 32, 0); > > + bitmap_set_value(old, 64, state[1], 32, 32); > > + state[0] = bitmap_get_value(new, 0, width[0]); > > + state[1] = bitmap_get_value(new, width[0], width[1]); > > + bitmap_set_value(new, 64, state[0], 32, 0); > > + bitmap_set_value(new, 64, state[1], 32, 32); > > + bitmap_xor(changed, old, new, 64); > > + > > + if (((u32 *)changed)[0]) > > + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, > > + state[0]); > > + if (((u32 *)changed)[1]) > > + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + > > + XGPIO_CHANNEL_OFFSET, state[1]); > > + > > + spin_unlock(&chip->gpio_lock[1]); > > + spin_unlock_irqrestore(&chip->gpio_lock[0], flags); > > } > > > > /** > > > > Srinivas N: Can you please test this code? > > Thanks, > Michal Hey, any chance of getting that Tested-by? Bart