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From:   Andy Lutomirski <luto@amacapital.net>
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Subject: Re: Why does glibc use AVX-512?
Date:   Fri, 26 Mar 2021 14:21:05 -0700
Message-Id: <C624A1B5-45EE-491C-B43B-5605D48273E9@amacapital.net>
References: <87pmzlboxj.fsf@mid.deneb.enyo.de>
Cc:     Andy Lutomirski <luto@kernel.org>,
        "H. J. Lu" <hjl.tools@gmail.com>, X86 ML <x86@kernel.org>,
        LKML <linux-kernel@vger.kernel.org>,
        "Bae, Chang Seok" <chang.seok.bae@intel.com>,
        Carlos O'Donell <carlos@redhat.com>,
        Rich Felker <dalias@libc.org>,
        libc-alpha <libc-alpha@sourceware.org>
In-Reply-To: <87pmzlboxj.fsf@mid.deneb.enyo.de>
To:     Florian Weimer <fw@deneb.enyo.de>
Precedence: bulk


> On Mar 26, 2021, at 2:11 PM, Florian Weimer <fw@deneb.enyo.de> wrote:
>=20
> =EF=BB=BF* Andy Lutomirski:
>=20
>>> On Fri, Mar 26, 2021 at 1:35 PM Florian Weimer <fw@deneb.enyo.de> wrote:=

>>>=20
>>> I mean the immense slowdown you get if you use %xmm registers after
> their %ymm counterparts (doesn't have to be %zmm, that issue is
> present starting with AVX) and you have not issued VZEROALL or
> VZEROUPPER between the two uses.

It turns out that it=E2=80=99s not necessary to access the registers in ques=
tion to trigger this behavior. You just need to make the CPU think it should=
 penalize you. For example, LDMXCSR appears to be a legacy SSE insn for this=
 purpose, and VLDMXCSR is an AVX insn for this purpose. I wouldn=E2=80=99t t=
rust that using ymm9 would avoid the penalty just because common sense says i=
t should.

>> What kind of system has that problem?
>=20
> It's a standard laptop after a suspend/resume cycle.  It's either a
> kernel or firmware bug.

What kernel version?  I think fixing the kernel makes more sense than fixing=
 glibc.