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From:   Bhaskar Chowdhury <unixbhaskar@gmail.com>
To:     corbet@lwn.net, linux-doc@vger.kernel.org
Cc:     Bhaskar Chowdhury <unixbhaskar@gmail.com>, rdunlap@infradead.org,
        linux-kernel@vger.kernel.org
Subject: [PATCH 22/23] riscv: pmu.rst : A spello fix
Date:   Mon, 29 Mar 2021 10:42:58 +0530
Message-Id: <5a7e9b80fe31c53b30337da0bdbd853d1b7afe5f.1616992679.git.unixbhaskar@gmail.com>
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s/resonable/reasonable/

Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
---
 Documentation/riscv/pmu.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/riscv/pmu.rst b/Documentation/riscv/pmu.rst
index acb216b99c26..fde31b6aa861 100644
--- a/Documentation/riscv/pmu.rst
+++ b/Documentation/riscv/pmu.rst
@@ -168,7 +168,7 @@ counter (event->count), but also updates the left period to the next interrupt
 But the core of perf does not need direct write to counters.  Writing counters
 is hidden behind the abstraction of 1) *pmu->start*, literally start counting so one
 has to set the counter to a good value for the next interrupt; 2) inside the IRQ
-it should set the counter to the same resonable value.
+it should set the counter to the same reasonable value.

 Reading is not a problem in RISC-V but writing would need some effort, since
 counters are not allowed to be written by S-mode.
--
2.26.3