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Message-ID: <f47350cef78ffbb65f7488d50bdb369d30daddef.camel@microchip.com>
Subject: Re: [PATCH v8 0/3] Adding the Sparx5 Switch Reset Driver
From:   Steen Hegelund <steen.hegelund@microchip.com>
To:     Philipp Zabel <p.zabel@pengutronix.de>
CC:     Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
        <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>
Date:   Mon, 29 Mar 2021 13:26:47 +0200
In-Reply-To: <20210316090839.3207930-1-steen.hegelund@microchip.com>
References: <20210316090839.3207930-1-steen.hegelund@microchip.com>
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Hi Philipp,

I just wanted to know if there are any outstanding items, or you think 
that the driver is acceptable as it is now?

BR
Steen

On Tue, 2021-03-16 at 10:08 +0100, Steen Hegelund wrote:
> This series provides the Microchip Sparx5 Switch Reset Driver
> 
> The Sparx5 Switch SoC has a number of components that can be reset
> individually, but at least the Switch Core needs to be in a well defined
> state at power on, when any of the Sparx5 drivers starts to access the
> Switch Core, this reset driver is available.
> 
> The reset driver is loaded early via the postcore_initcall interface, and
> will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc)
> that are loaded next, and the first of them to be loaded can perform the
> one-time Switch Core reset that is needed.
> 
> The driver has protection so that the system busses, DDR controller, PCI-E
> and ARM A53 CPU and a few other subsystems are not touched by the reset.
> 
> Sparx5 will no longer use the existing Ocelot chip reset driver, but use
> this new switch reset driver as it has the reset controller interface that
> allows the first client to perform the reset on behalf of all the Sparx5
> component drivers.
> 
> The Sparx5 Chip Register Model can be browsed at this location:
> https://github.com/microchip-ung/sparx-5_reginfo
> and the datasheet is available here:
> https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Switches_Datasheet_00003822B.pdf
> 
> History:
> 
> v7 -> v8 Updated the commit descriptions to explain the change from using
>          the existing Ocelot chip reset driver to use a new switch reset
>          driver.
> 
> v6 -> v7 Use devm_platform_get_and_ioremap_resource to get the IO range.
>          Rebase on v5.12-rc1
> 
> v5 -> v6 Using the existing CPU syscon for reset protection and add a small
>          IO range for the GCB Reset Register.
> 
> v4 -> v5 Changed the two syscons into IO ranges and updated the bindings to
>          reflect this change.
> 
> v3 -> v4 Added commit message descriptions
> 
> v2 -> v3 Removed unused headers
>          Renamed the reset controller dev member.
>          Use regmap_read_poll_timeout instead of polling a function.
>          Used two separate syscon entries in the binding
>          Simplified the syscon error handling.
>          Simplified the devm_reset_controller_register error handling.
>          Moved the contents of the mchp_sparx5_reset_config function into
>          the probe function.
> 
> v1 -> v2 Removed debug prints
>          Changed the error handling to save the error code before jumping.
> 
> Steen Hegelund (3):
>   dt-bindings: reset: microchip sparx5 reset driver bindings
>   reset: mchp: sparx5: add switch reset driver
>   arm64: dts: reset: add microchip sparx5 switch reset driver
> 
>  .../bindings/reset/microchip,rst.yaml         |  58 +++++++
>  arch/arm64/boot/dts/microchip/sparx5.dtsi     |   7 +-
>  drivers/reset/Kconfig                         |   8 +
>  drivers/reset/Makefile                        |   1 +
>  drivers/reset/reset-microchip-sparx5.c        | 146 ++++++++++++++++++
>  5 files changed, 218 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
>  create mode 100644 drivers/reset/reset-microchip-sparx5.c
>