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Date:   Mon, 29 Mar 2021 16:58:43 +0100
From:   Mark Brown <broonie@kernel.org>
To:     Brad Larson <brad@pensando.io>
Cc:     linux-arm-kernel@lists.infradead.org, arnd@arndb.de,
        linus.walleij@linaro.org, bgolaszewski@baylibre.com,
        fancer.lancer@gmail.com, adrian.hunter@intel.com,
        ulf.hansson@linaro.org, olof@lixom.net, linux-gpio@vger.kernel.org,
        linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 03/13] spi: dw: Add support for Pensando Elba SoC SPI
Message-ID: <20210329155843.GD5166@sirena.org.uk>
References: <20210329015938.20316-1-brad@pensando.io>
 <20210329015938.20316-4-brad@pensando.io>
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On Sun, Mar 28, 2021 at 06:59:28PM -0700, Brad Larson wrote:

> @@ -56,7 +56,7 @@ struct dw_spi_mscc {
>  /*
>   * The Designware SPI controller (referred to as master in the documenta=
tion)
>   * automatically deasserts chip select when the tx fifo is empty. The ch=
ip
> - * selects then needs to be either driven as GPIOs or, for the first 4 u=
sing the
> + * selects then needs to be either driven as GPIOs or, for the first 4 u=
sing
>   * the SPI boot controller registers. the final chip select is an OR gate
>   * between the Designware SPI controller and the SPI boot controller.
>   */

This is an unrelated fix, please send as a separate patch as covered in
submitting-patches.rst.

> @@ -237,6 +237,31 @@ static int dw_spi_canaan_k210_init(struct platform_d=
evice *pdev,
>  	return 0;
>  }
> =20
> +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
> +{
> +	struct dw_spi *dws =3D spi_master_get_devdata(spi->master);
> +
> +	if (!enable) {
> +		/*
> +		 * Using a GPIO-based chip-select, the DW SPI
> +		 * controller still needs its own CS bit selected
> +		 * to start the serial engine.  On Elba the specific
> +		 * CS doesn't matter to start the serial engine,
> +		 * so using CS0.
> +		 */

Why does this comment only apply to one branch of the conditional?

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