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Tue, 30 Mar 2021 12:55:06 +0000 Subject: Re: [PATCH] drm/amdgpu: fix an underflow on non-4KB-page systems To: Xi Ruoyao , =?UTF-8?Q?Christian_K=c3=b6nig?= , Alex Deucher Cc: David Airlie , Felix Kuehling , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, =?UTF-8?Q?Dan_Hor=c3=a1k?= , amd-gfx@lists.freedesktop.org, Daniel Vetter , stable@vger.kernel.org References: <20210329175348.26859-1-xry111@mengyan1223.wang> <9a11c873-a362-b5d1-6d9c-e937034e267d@gmail.com> <84b3911173ad6beb246ba0a77f93d888ee6b393e.camel@mengyan1223.wang> <97c520ce107aa4d5fd96e2c380c8acdb63d45c37.camel@mengyan1223.wang> <7701fb71-9243-2d90-e1e1-d347a53b7d77@gmail.com> <368b9b1b7343e35b446bb1028ccf0ae75dc2adc4.camel@mengyan1223.wang> <71e3905a5b72c5b97df837041b19175540ebb023.camel@mengyan1223.wang> From: =?UTF-8?Q?Christian_K=c3=b6nig?= Message-ID: Date: Tue, 30 Mar 2021 14:55:01 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 In-Reply-To: <71e3905a5b72c5b97df837041b19175540ebb023.camel@mengyan1223.wang> Content-Type: text/plain; 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>>>> >>>> /* snip */ >>>> >>>>          saddr /= AMDGPU_GPU_PAGE_SIZE; >>>>          eaddr /= AMDGPU_GPU_PAGE_SIZE; >>>> >>>> /* snip */ >>>> >>>>          mapping->start = saddr; >>>>          mapping->last = eaddr; >>>> >>>> >>>> If we really want to ensure (mapping->last - mapping->start + 1) % >>>> AMDGPU_GPU_PAGES_IN_CPU_PAGE == 0, then we should replace >>>> "AMDGPU_GPU_PAGE_MASK" >>>> in "validate the parameters" with "PAGE_MASK". > It should be "~PAGE_MASK", "PAGE_MASK" has an opposite convention of > "AMDGPU_GPU_PAGE_MASK" :(. > >>> Yeah, good point. >>> >>>> I tried it and it broke userspace: Xorg startup fails with EINVAL with >>>> this >>>> change. >>> Well in theory it is possible that we always fill the GPUVM on a 4k >>> basis while the native page size of the CPU is larger. Let me double >>> check the code. > On my platform, there are two issues both causing the VM corruption. One is > fixed by agd5f/linux@fe001e7. What is fe001e7? A commit id? If yes then that is to short and I can't find it. > Another is in Mesa from userspace: it uses > `dev_info->gart_page_size` as the alignment, but the kernel AMDGPU driver > expects it to use `dev_info->virtual_address_alignment`. Mhm, looking at the kernel code I would rather say Mesa is correct and the kernel driver is broken. The gart_page_size is limited by the CPU page size, but the virtual_address_alignment isn't. > If we can make the change to fill the GPUVM on a 4k basis, we can fix this issue > and make virtual_address_alignment = 4K. Otherwise, we should fortify the > parameter validation, changing "AMDGPU_GPU_PAGE_MASK" to "~PAGE_MASK". Then the > userspace will just get an EINVAL, instead of a slient VM corruption. And > someone should tell Mesa developers to fix the code in this case. I rather see this as a kernel bug. Can you test if this code fragment fixes your issue: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 64beb3399604..e1260b517e1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -780,7 +780,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)                 }                 dev_info->virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; -               dev_info->gart_page_size = AMDGPU_GPU_PAGE_SIZE; +               dev_info->gart_page_size = dev_info->virtual_address_alignment;                 dev_info->cu_active_number = adev->gfx.cu_info.number;                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;                 dev_info->ce_ram_size = adev->gfx.ce_ram_size; Thanks, Christian. > -- > Xi Ruoyao > School of Aerospace Science and Technology, Xidian University >