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[23.128.96.18]) by mx.google.com with ESMTP id d13si9320744edy.407.2021.03.30.07.48.21; Tue, 30 Mar 2021 07:48:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231622AbhC3OrW (ORCPT + 99 others); Tue, 30 Mar 2021 10:47:22 -0400 Received: from mga12.intel.com ([192.55.52.136]:47223 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232064AbhC3OrI (ORCPT ); Tue, 30 Mar 2021 10:47:08 -0400 IronPort-SDR: J9yBuda1HYbxxBtE54/H5sxJYew9LTSzeQ8ySnai9fpUFQqnHQuQw58OY6kGMDfFyLkhcEs4NS Y6qaYL7NzOrQ== X-IronPort-AV: E=McAfee;i="6000,8403,9939"; a="171189797" X-IronPort-AV: E=Sophos;i="5.81,291,1610438400"; d="gz'50?scan'50,208,50";a="171189797" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2021 07:46:51 -0700 IronPort-SDR: GyeuM3fvxQhLBAgiPKggt6Jh4AjrrFUz4xUQEKBB6Q7lriTzPFQnyY/GNN/Td1TTs9PAuGqxFP ux8hLzWXKQYA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,291,1610438400"; d="gz'50?scan'50,208,50";a="378514121" Received: from lkp-server01.sh.intel.com (HELO 69d8fcc516b7) ([10.239.97.150]) by orsmga006.jf.intel.com with ESMTP; 30 Mar 2021 07:46:47 -0700 Received: from kbuild by 69d8fcc516b7 with local (Exim 4.92) (envelope-from ) id 1lRFdn-0005KI-4o; Tue, 30 Mar 2021 14:46:47 +0000 Date: Tue, 30 Mar 2021 22:45:44 +0800 From: kernel test robot To: Andy Shevchenko , Wolfram Sang , Serge Semin , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Cc: kbuild-all@lists.01.org, Jarkko Nikula , Mika Westerberg , Yicong Yang Subject: Re: [PATCH v1 1/1] i2c: designware: Switch over to i2c_freq_mode_string() Message-ID: <202103302210.r6wUfKqW-lkp@intel.com> References: <20210330134633.29889-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="KsGdsel6WgEHnImy" Content-Disposition: inline In-Reply-To: <20210330134633.29889-1-andriy.shevchenko@linux.intel.com> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --KsGdsel6WgEHnImy Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Andy, I love your patch! Yet something to improve: [auto build test ERROR on wsa/i2c/for-next] [also build test ERROR on v5.12-rc5 next-20210330] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Andy-Shevchenko/i2c-designware-Switch-over-to-i2c_freq_mode_string/20210330-214856 base: https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git i2c/for-next config: parisc-randconfig-r021-20210330 (attached as .config) compiler: hppa-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/fc212e73959cd6616bd734027805962593a28d9a git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Andy-Shevchenko/i2c-designware-Switch-over-to-i2c_freq_mode_string/20210330-214856 git checkout fc212e73959cd6616bd734027805962593a28d9a # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=parisc If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All error/warnings (new ones prefixed by >>): In file included from include/linux/device.h:15, from include/linux/acpi.h:15, from include/linux/i2c.h:13, from drivers/i2c/busses/i2c-designware-master.c:16: drivers/i2c/busses/i2c-designware-master.c: In function 'i2c_dw_set_timings_master': >> drivers/i2c/busses/i2c-designware-master.c:158:39: error: implicit declaration of function 'i2c_freq_mode_string' [-Werror=implicit-function-declaration] 158 | dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); | ^~~~~~~~~~~~~~~~~~~~ include/linux/dev_printk.h:126:46: note: in definition of macro 'dev_dbg' 126 | dev_printk(KERN_DEBUG, dev, dev_fmt(fmt), ##__VA_ARGS__) | ^~~~~~~~~~~ >> drivers/i2c/busses/i2c-designware-master.c:158:20: warning: format '%s' expects argument of type 'char *', but argument 4 has type 'int' [-Wformat=] 158 | dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); | ^~~~~~~~~~~~~~~~~ include/linux/dev_printk.h:19:22: note: in definition of macro 'dev_fmt' 19 | #define dev_fmt(fmt) fmt | ^~~ drivers/i2c/busses/i2c-designware-master.c:158:2: note: in expansion of macro 'dev_dbg' 158 | dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); | ^~~~~~~ drivers/i2c/busses/i2c-designware-master.c:158:33: note: format string is defined here 158 | dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); | ~^ | | | char * | %d cc1: some warnings being treated as errors vim +/i2c_freq_mode_string +158 drivers/i2c/busses/i2c-designware-master.c 35 36 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev) 37 { 38 u32 comp_param1; 39 u32 sda_falling_time, scl_falling_time; 40 struct i2c_timings *t = &dev->timings; 41 const char *fp_str = ""; 42 u32 ic_clk; 43 int ret; 44 45 ret = i2c_dw_acquire_lock(dev); 46 if (ret) 47 return ret; 48 49 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); 50 i2c_dw_release_lock(dev); 51 if (ret) 52 return ret; 53 54 /* Set standard and fast speed dividers for high/low periods */ 55 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ 56 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ 57 58 /* Calculate SCL timing parameters for standard mode if not set */ 59 if (!dev->ss_hcnt || !dev->ss_lcnt) { 60 ic_clk = i2c_dw_clk_rate(dev); 61 dev->ss_hcnt = 62 i2c_dw_scl_hcnt(ic_clk, 63 4000, /* tHD;STA = tHIGH = 4.0 us */ 64 sda_falling_time, 65 0, /* 0: DW default, 1: Ideal */ 66 0); /* No offset */ 67 dev->ss_lcnt = 68 i2c_dw_scl_lcnt(ic_clk, 69 4700, /* tLOW = 4.7 us */ 70 scl_falling_time, 71 0); /* No offset */ 72 } 73 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n", 74 dev->ss_hcnt, dev->ss_lcnt); 75 76 /* 77 * Set SCL timing parameters for fast mode or fast mode plus. Only 78 * difference is the timing parameter values since the registers are 79 * the same. 80 */ 81 if (t->bus_freq_hz == 1000000) { 82 /* 83 * Check are Fast Mode Plus parameters available. Calculate 84 * SCL timing parameters for Fast Mode Plus if not set. 85 */ 86 if (dev->fp_hcnt && dev->fp_lcnt) { 87 dev->fs_hcnt = dev->fp_hcnt; 88 dev->fs_lcnt = dev->fp_lcnt; 89 } else { 90 ic_clk = i2c_dw_clk_rate(dev); 91 dev->fs_hcnt = 92 i2c_dw_scl_hcnt(ic_clk, 93 260, /* tHIGH = 260 ns */ 94 sda_falling_time, 95 0, /* DW default */ 96 0); /* No offset */ 97 dev->fs_lcnt = 98 i2c_dw_scl_lcnt(ic_clk, 99 500, /* tLOW = 500 ns */ 100 scl_falling_time, 101 0); /* No offset */ 102 } 103 fp_str = " Plus"; 104 } 105 /* 106 * Calculate SCL timing parameters for fast mode if not set. They are 107 * needed also in high speed mode. 108 */ 109 if (!dev->fs_hcnt || !dev->fs_lcnt) { 110 ic_clk = i2c_dw_clk_rate(dev); 111 dev->fs_hcnt = 112 i2c_dw_scl_hcnt(ic_clk, 113 600, /* tHD;STA = tHIGH = 0.6 us */ 114 sda_falling_time, 115 0, /* 0: DW default, 1: Ideal */ 116 0); /* No offset */ 117 dev->fs_lcnt = 118 i2c_dw_scl_lcnt(ic_clk, 119 1300, /* tLOW = 1.3 us */ 120 scl_falling_time, 121 0); /* No offset */ 122 } 123 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n", 124 fp_str, dev->fs_hcnt, dev->fs_lcnt); 125 126 /* Check is high speed possible and fall back to fast mode if not */ 127 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == 128 DW_IC_CON_SPEED_HIGH) { 129 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK) 130 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) { 131 dev_err(dev->dev, "High Speed not supported!\n"); 132 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; 133 dev->master_cfg |= DW_IC_CON_SPEED_FAST; 134 dev->hs_hcnt = 0; 135 dev->hs_lcnt = 0; 136 } else if (!dev->hs_hcnt || !dev->hs_lcnt) { 137 ic_clk = i2c_dw_clk_rate(dev); 138 dev->hs_hcnt = 139 i2c_dw_scl_hcnt(ic_clk, 140 160, /* tHIGH = 160 ns */ 141 sda_falling_time, 142 0, /* DW default */ 143 0); /* No offset */ 144 dev->hs_lcnt = 145 i2c_dw_scl_lcnt(ic_clk, 146 320, /* tLOW = 320 ns */ 147 scl_falling_time, 148 0); /* No offset */ 149 } 150 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n", 151 dev->hs_hcnt, dev->hs_lcnt); 152 } 153 154 ret = i2c_dw_set_sda_hold(dev); 155 if (ret) 156 return ret; 157 > 158 dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); 159 return 0; 160 } 161 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org --KsGdsel6WgEHnImy Content-Type: application/gzip Content-Disposition: attachment; filename=".config.gz" Content-Transfer-Encoding: base64 H4sICNwyY2AAAy5jb25maWcAlDxrb+O2st/7K4QtcNECTdd2kt0NLvKBoiibtSSqIuUo+SK4 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