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[23.128.96.18]) by mx.google.com with ESMTP id r15si1689397eji.282.2021.03.31.06.35.20; Wed, 31 Mar 2021 06:35:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=zESha82x; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235809AbhCaNde (ORCPT + 99 others); Wed, 31 Mar 2021 09:33:34 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:35582 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235784AbhCaNdN (ORCPT ); Wed, 31 Mar 2021 09:33:13 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12VDWbfT128296; Wed, 31 Mar 2021 08:32:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1617197557; bh=YYcWMd00SGs3crRbWxcFqADJOgyNtBSyyx4h5FCJOLU=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=zESha82xuGVQgBYnpa0qk9GVYZ7gXXdsuOh/KJKx82e6XU/CIjU6lCoMF/ZNlz7TL sw4UyFR0i0hWIxSEOImDpLNTnk/c1N2rb2vdgxUr/MujIUlexmNjjd9COB7g0qT4+x Ar4nkUtW6HYrk/8Iyv+0FoJF+eGQVpYRJ6dqJ09o= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12VDWbc2119028 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Mar 2021 08:32:37 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 31 Mar 2021 08:32:37 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 31 Mar 2021 08:32:36 -0500 Received: from [10.250.234.114] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12VDWUVw091817; Wed, 31 Mar 2021 08:32:30 -0500 Subject: Re: [PATCH v5 2/5] phy: Add LVDS configuration options To: Liu Ying , , , , CC: , , , , , , , , , , , , , , , , , References: <1616662832-27048-1-git-send-email-victor.liu@nxp.com> <1616662832-27048-3-git-send-email-victor.liu@nxp.com> From: Kishon Vijay Abraham I Message-ID: Date: Wed, 31 Mar 2021 19:02:29 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <1616662832-27048-3-git-send-email-victor.liu@nxp.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 25/03/21 2:30 pm, Liu Ying wrote: > This patch allows LVDS PHYs to be configured through > the generic functions and through a custom structure > added to the generic union. > > The parameters added here are based on common LVDS PHY > implementation practices. The set of parameters > should cover all potential users. > > Cc: Kishon Vijay Abraham I > Cc: Vinod Koul > Cc: NXP Linux Team > Signed-off-by: Liu Ying > --- > v4->v5: > * Align kernel-doc style to include/linux/phy/phy.h. (Vinod) > * Trivial tweaks. > * Drop Robert's R-b tag. > > v3->v4: > * Add Robert's R-b tag. > > v2->v3: > * No change. > > v1->v2: > * No change. > > include/linux/phy/phy-lvds.h | 32 ++++++++++++++++++++++++++++++++ > include/linux/phy/phy.h | 4 ++++ > 2 files changed, 36 insertions(+) > create mode 100644 include/linux/phy/phy-lvds.h > > diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h > new file mode 100644 > index 00000000..7a2f474 > --- /dev/null > +++ b/include/linux/phy/phy-lvds.h > @@ -0,0 +1,32 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright 2020 NXP > + */ > + > +#ifndef __PHY_LVDS_H_ > +#define __PHY_LVDS_H_ > + > +/** > + * struct phy_configure_opts_lvds - LVDS configuration set > + * @bits_per_lane_and_dclk_cycle: Number of bits per data lane and > + * differential clock cycle. phy_set_bus_width() instead? > + * @differential_clk_rate: Clock rate, in Hertz, of the LVDS > + * differential clock. Please use clk API's to get rate. > + * @lanes: Number of active, consecutive, > + * data lanes, starting from lane 0, > + * used for the transmissions. > + * @is_slave: Boolean, true if the phy is a slave > + * which works together with a master > + * phy to support dual link transmission, > + * otherwise a regular phy or a master phy. For parameters that are known at design time, it doesn't have to be passed from consumer driver. So all these parameters do they really have to be passed at runtime? Thanks Kishon > + * > + * This structure is used to represent the configuration state of a LVDS phy. > + */ > +struct phy_configure_opts_lvds { > + unsigned int bits_per_lane_and_dclk_cycle; > + unsigned long differential_clk_rate; > + unsigned int lanes; > + bool is_slave; > +}; > + > +#endif /* __PHY_LVDS_H_ */ > diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h > index e435bdb..d450b44 100644 > --- a/include/linux/phy/phy.h > +++ b/include/linux/phy/phy.h > @@ -17,6 +17,7 @@ > #include > > #include > +#include > #include > > struct phy; > @@ -51,10 +52,13 @@ enum phy_mode { > * the MIPI_DPHY phy mode. > * @dp: Configuration set applicable for phys supporting > * the DisplayPort protocol. > + * @lvds: Configuration set applicable for phys supporting > + * the LVDS phy mode. > */ > union phy_configure_opts { > struct phy_configure_opts_mipi_dphy mipi_dphy; > struct phy_configure_opts_dp dp; > + struct phy_configure_opts_lvds lvds; > }; > > /** >