Received: by 2002:a05:6a10:9848:0:0:0:0 with SMTP id x8csp502725pxf; Wed, 31 Mar 2021 08:40:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwzZVMATmGdwjANpaYLWPVgh9JlTYz1eTdwJUboNkdeYmoMCIGQo/wpm9vA2bcY9gnh4FTX X-Received: by 2002:a17:906:358c:: with SMTP id o12mr4296380ejb.156.1617205222716; Wed, 31 Mar 2021 08:40:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617205222; cv=none; d=google.com; s=arc-20160816; b=NrQYLsBHIbvTmDLvAE4PXLbnj14rWgoa1ZK6QHKcK0H1zDc8QRes+VC3goOV37L2Db lovs6wtYLU7hdB6Krrq31rNuwV6RrbaFD4Zk/8k3f42JNX1yl7whEycBmAmrpVqgQprA 0cCt++JGL7V1Ros4czQfFoy74J0JmXBI2FkvfCmPL44Gs4QBPBje2cB2+qWsxiSSwhCV C0Kgm6rvbfgzS7IMEcyzx4M9g5zzIIdCVHIgICpiZU9/V6SANA5pB5yOSdrxLG+u/wZJ H/dQXIyf9AMVOn3rpNaimmPP4INzx5mIIQfQPnCHET2orUNs9J52TmDPN3SHrekIRSir G+IQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :dkim-signature; bh=I87M0AMjpujynCtT+ZLXMQDNj8u42EDcLtz3ASGa3wo=; b=ncJkDDQSwg3wU2FO4AL1cQIMwKTT8IS+xrRp7RrukYKzrNJP7TNwYzn2KfLz/pfOIU hnbjnq/Cd6iEGgW7UddDdfqpMlgrhUzt7e1k89/VCtCEc6H0Ne0ueq+jOtN1xfmMBfV7 dZ4MGMOwjQ4QYUUaLuNKubrMZL73Hj8gpxT5twkJIJWnhW/pmKiIKbKyyHgMLcE86YDP 9xVSrEXwraEJQzIsPNsqkPd5HmY/TaJy3NjHNKTOSSe8/nEs1Vu92RwSTyn7MsuB3R3X nbnZvD8onFvBMNmpVTl7Np2YYHwO+8uHwGvgFepjxguAPwzzaJWVgmdf9gaIWlS7rnmT LsHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=kXb8HMKz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bs6si2110704edb.145.2021.03.31.08.39.58; Wed, 31 Mar 2021 08:40:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=kXb8HMKz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235694AbhCaPjC (ORCPT + 99 others); Wed, 31 Mar 2021 11:39:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:60960 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236421AbhCaPiw (ORCPT ); Wed, 31 Mar 2021 11:38:52 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6CF1D60FED; Wed, 31 Mar 2021 15:38:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1617205132; bh=zSKNNt8aHpVOX7T1mrGusbLW0X9P8mDEBnTRjCK5rWs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=kXb8HMKzNCMDmWEsyoz6cYK42VRs7763h3dgrABPa04VRqfZx0PIX+QlCr3xM30bG FXGIk8u9jl0Ks0KwB4Vtqqh4HJuhOOIM2TwuZ2lLhC35GkLsZwH+tGLxETrlvB/Xbq rN60C/MqtfB4tnmo9f1b3sCq8P/hOCh1F56NdYn9UWpHMpLb/Ts6vEPDWrIu7JDKfD nD8lMH5xZ7mm7ZK0sSTktM/1hcsEMINzyxc2toeRFA0hogjvHlXyX6dj2xYZV13N8S 8hE3OIteR2wcc+0ePV3Zkros/1XNZERWRn0EhiQ/XTxMHZoNN3uXyg5zuRuYDQHm8w lF9TNTJX//avw== Date: Wed, 31 Mar 2021 16:38:46 +0100 From: Will Deacon To: Rob Herring Cc: Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Jiri Olsa , Mark Rutland , Ian Rogers , Alexander Shishkin , Honnappa Nagarahalli , Zachary.Leaf@arm.com, Raphael Gault , Jonathan Cameron , Namhyung Kim , Itaru Kitayama , linux-arm-kernel , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v6 02/10] arm64: perf: Enable PMU counter direct access for perf event Message-ID: <20210331153845.GB7815@willie-the-truck> References: <20210311000837.3630499-1-robh@kernel.org> <20210311000837.3630499-3-robh@kernel.org> <20210330153125.GC6567@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 30, 2021 at 04:08:11PM -0500, Rob Herring wrote: > On Tue, Mar 30, 2021 at 12:09 PM Rob Herring wrote: > > On Tue, Mar 30, 2021 at 10:31 AM Will Deacon wrote: > > > The logic here feels like it > > > could with a bit of untangling. > > > > Yes, I don't love it, but couldn't come up with anything better. It is > > complicated by the fact that flags have to be set before we assign the > > counter and can't set/change them when we assign the counter. It would > > take a lot of refactoring with armpmu code to fix that. > > How's this instead?: > > if (armv8pmu_event_want_user_access(event) || !armv8pmu_event_is_64bit(event)) > event->hw.flags |= ARMPMU_EL0_RD_CNTR; > > /* > * At this point, the counter is not assigned. If a 64-bit counter is > * requested, we must make sure the h/w has 64-bit counters if we set > * the event size to 64-bit because chaining is not supported with > * userspace access. This may still fail later on if the CPU cycle > * counter is in use. > */ > if (armv8pmu_event_is_64bit(event) && > (!armv8pmu_event_want_user_access(event) || > armv8pmu_has_long_event(cpu_pmu) || (hw_event_id == > ARMV8_PMUV3_PERFCTR_CPU_CYCLES))) > event->hw.flags |= ARMPMU_EVT_64BIT; I thought there were some cases where we could assign cycles event to an event counter; does that not happen anymore? Will