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Box" To: irenic.rajneesh@gmail.com, hdegoede@redhat.com, david.e.box@linux.intel.com, mgross@linux.intel.com, gayatri.kammela@intel.com Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/9] intel_pmc_core: Add sub-state requirements and mode latching support Date: Wed, 31 Mar 2021 20:05:49 -0700 Message-Id: <20210401030558.2301621-1-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org - Patch 1 and 2 remove the use of the global struct pmc_dev - Patches 3-7 add support for reading low power mode sub-state requirements, latching sub-state status on different low power mode events, and displaying the sub-state residency in microseconds - Patch 8 adds missing LTR IPs for TGL - Patch 9 adds support for ADL-P which is based on TGL Applied on top of latest 5.12-rc2 based hans-review/review-hans David E. Box (4): platform/x86: intel_pmc_core: Don't use global pmcdev in quirks platform/x86: intel_pmc_core: Remove global struct pmc_dev platform/x86: intel_pmc_core: Add option to set/clear LPM mode platform/x86: intel_pmc_core: Add support for Alder Lake PCH-P Gayatri Kammela (5): platform/x86: intel_pmc_core: Handle sub-states generically platform/x86: intel_pmc_core: Show LPM residency in microseconds platform/x86: intel_pmc_core: Get LPM requirements for Tiger Lake platform/x86: intel_pmc_core: Add requirements file to debugfs platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake drivers/platform/x86/intel_pmc_core.c | 359 +++++++++++++++++++++++--- drivers/platform/x86/intel_pmc_core.h | 47 +++- 2 files changed, 370 insertions(+), 36 deletions(-) -- 2.25.1