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[23.128.96.18]) by mx.google.com with ESMTP id j10si3738317ejs.618.2021.03.31.23.16.05; Wed, 31 Mar 2021 23:16:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=huawei.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233143AbhDAGMs (ORCPT + 99 others); Thu, 1 Apr 2021 02:12:48 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:15841 "EHLO szxga07-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232994AbhDAGMU (ORCPT ); Thu, 1 Apr 2021 02:12:20 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4F9t7w29PWz9v7J; Thu, 1 Apr 2021 14:10:04 +0800 (CST) Received: from [10.174.185.179] (10.174.185.179) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.498.0; Thu, 1 Apr 2021 14:12:02 +0800 Subject: Re: [PATCH v14 07/13] iommu/smmuv3: Implement cache_invalidate To: Eric Auger CC: , , , , , , , , , , , , , , , , , , , , , , , , References: <20210223205634.604221-1-eric.auger@redhat.com> <20210223205634.604221-8-eric.auger@redhat.com> From: Zenghui Yu Message-ID: <95a178f0-fc84-b9a2-d824-c09ea91c9d30@huawei.com> Date: Thu, 1 Apr 2021 14:11:59 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: <20210223205634.604221-8-eric.auger@redhat.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.185.179] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Eric, On 2021/2/24 4:56, Eric Auger wrote: > +static int > +arm_smmu_cache_invalidate(struct iommu_domain *domain, struct device *dev, > + struct iommu_cache_invalidate_info *inv_info) > +{ > + struct arm_smmu_cmdq_ent cmd = {.opcode = CMDQ_OP_TLBI_NSNH_ALL}; > + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + > + if (smmu_domain->stage != ARM_SMMU_DOMAIN_NESTED) > + return -EINVAL; > + > + if (!smmu) > + return -EINVAL; > + > + if (inv_info->version != IOMMU_CACHE_INVALIDATE_INFO_VERSION_1) > + return -EINVAL; > + > + if (inv_info->cache & IOMMU_CACHE_INV_TYPE_PASID || I didn't find any code where we would emulate the CFGI_CD{_ALL} commands for guest and invalidate the stale CD entries on the physical side. Is PASID-cache type designed for that effect? > + inv_info->cache & IOMMU_CACHE_INV_TYPE_DEV_IOTLB) { > + return -ENOENT; > + } > + > + if (!(inv_info->cache & IOMMU_CACHE_INV_TYPE_IOTLB)) > + return -EINVAL; > + > + /* IOTLB invalidation */ > + > + switch (inv_info->granularity) { > + case IOMMU_INV_GRANU_PASID: > + { > + struct iommu_inv_pasid_info *info = > + &inv_info->granu.pasid_info; > + > + if (info->flags & IOMMU_INV_ADDR_FLAGS_PASID) > + return -ENOENT; > + if (!(info->flags & IOMMU_INV_PASID_FLAGS_ARCHID)) > + return -EINVAL; > + > + __arm_smmu_tlb_inv_context(smmu_domain, info->archid); > + return 0; > + } > + case IOMMU_INV_GRANU_ADDR: > + { > + struct iommu_inv_addr_info *info = &inv_info->granu.addr_info; > + size_t size = info->nb_granules * info->granule_size; > + bool leaf = info->flags & IOMMU_INV_ADDR_FLAGS_LEAF; > + > + if (info->flags & IOMMU_INV_ADDR_FLAGS_PASID) > + return -ENOENT; > + > + if (!(info->flags & IOMMU_INV_ADDR_FLAGS_ARCHID)) > + break; > + > + arm_smmu_tlb_inv_range_domain(info->addr, size, > + info->granule_size, leaf, > + info->archid, smmu_domain); > + > + arm_smmu_cmdq_issue_sync(smmu); There is no need to issue one more SYNC.