Received: by 2002:a05:6a10:9848:0:0:0:0 with SMTP id x8csp254390pxf; Wed, 31 Mar 2021 23:41:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwUd5r7IOtDAueNsLfoUQxzZIsw1z6pkhw++A9e9SkLBQqXo5MqSFVi8GwFxqt8vJ7XCsg9 X-Received: by 2002:a05:6402:1c98:: with SMTP id cy24mr8112733edb.296.1617259270124; Wed, 31 Mar 2021 23:41:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617259270; cv=none; d=google.com; s=arc-20160816; b=fBFX9WhWMo1IlYdkmbqhCKwD0st9WqpCLcMd/kXiIico2oKa+/PFCemRAb1YhfMnre V75nKh8JOESbQIVpfSKd8GRsHZIGttmY2zSrg6+xqrNk7P62MFYuIH7gycrawSpfLloN jo2CiofcKpGVY4nSdHtTBkPZTsnp2HVPlMJbSFRNgv1ooEIVKxWzR3nlH1VF1oIcuP3n wY94Llx8kOXxJwRzXDUYXOkEYYqH89UKRz5TR/MMAuVAOoLLvEyPVhFHYmqca1/LWBjz BVG7YrrFrfkqqDZZgvW3jkk51JTAoBjcVbVEzPaftsWpPGMxYddRN5yDk+YeINrnVOZg G/KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=Czcsqtc/Q8iNa2iv32eqMNTZkI3dgkWPxzWKuoO3Dmc=; b=nus0grAl7P3vWad2G6+fx9WNERviHRY5e2NUyNxEhD2yEZ9ArAP+uCQapU3zx2yd3v OrC1G43WfXRbs+W6mkmDQmq5NDlOtk1nK5dXOZoITbgWPMkqPmLDLboFqDi3bU5lQAEf 9q2+YLfdrzdRTkV9rhKR/+JVYmgXBFAmuaqCHPWA877i+qXC4ObLEN+Kt5y+z8iStymA Ol5SD+3UDPToFh5WIyBho/WcAw4AyvUNfZlJGP7QNYg/fZ9Q7McQE0bkjq6TA+7jyCbX EDIBylkCv8eFGiydMTeL8Ad/uAarklhTxcXPh9q9w7jFOcXskmToYMr6DQdpCe6YKek7 qEWQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id m9si3339208ejr.535.2021.03.31.23.40.48; Wed, 31 Mar 2021 23:41:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233407AbhDAGjw (ORCPT + 99 others); Thu, 1 Apr 2021 02:39:52 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:41440 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229539AbhDAGjR (ORCPT ); Thu, 1 Apr 2021 02:39:17 -0400 X-UUID: 066aaf53bd90488995aeaacb876a3e0e-20210401 X-UUID: 066aaf53bd90488995aeaacb876a3e0e-20210401 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 380086253; Thu, 01 Apr 2021 14:39:12 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 1 Apr 2021 14:39:08 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 1 Apr 2021 14:39:09 +0800 From: Nina Wu To: Rob Herring , Matthias Brugger CC: Nina Wu , Zhen Lei , Neal Liu , , , , , , Subject: [PATCH v2 1/6] dt-bindings: devapc: Update bindings Date: Thu, 1 Apr 2021 14:38:02 +0800 Message-ID: <1617259087-5502-1-git-send-email-nina-cm.wu@mediatek.com> X-Mailer: git-send-email 2.6.4 MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 580A08974BAFC9A6A81C47BC47B66CEFAAC52E26F7B27EACDDAD88708ABEC6EC2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Nina Wu To support newer hardware architecture of devapc, update device tree bindings. Signed-off-by: Nina Wu --- Documentation/devicetree/bindings/soc/mediatek/devapc.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml index 31e4d3c..42b284e 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml @@ -20,11 +20,17 @@ properties: compatible: enum: - mediatek,mt6779-devapc + - mediatek,mt8192-devapc reg: description: The base address of devapc register bank maxItems: 1 + vio-idx-num: + description: The number of the devices controlled by devapc + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + interrupts: description: A single interrupt specifier maxItems: 1 @@ -40,6 +46,7 @@ properties: required: - compatible - reg + - vio-idx-num - interrupts - clocks - clock-names @@ -54,6 +61,7 @@ examples: devapc: devapc@10207000 { compatible = "mediatek,mt6779-devapc"; reg = <0x10207000 0x1000>; + vio-idx-num = <511>; interrupts = ; clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>; clock-names = "devapc-infra-clock"; -- 2.6.4