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Subject: Re: [PATCH 4/4] dt-bindings: spi: Convert cadence-quadspi.txt to
 cadence-quadspi.yaml
To:     Pratyush Yadav <p.yadav@ti.com>, Rob Herring <robh@kernel.org>
CC:     Mark Brown <broonie@kernel.org>, Nishanth Menon <nm@ti.com>,
        Tero Kristo <kristo@kernel.org>, <linux-spi@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>
References: <20210326130034.15231-1-p.yadav@ti.com>
 <20210326130034.15231-5-p.yadav@ti.com>
 <20210327183628.GA345487@robh.at.kernel.org>
 <20210329182256.q4zhss6lezj3s44a@ti.com>
From:   Vignesh Raghavendra <vigneshr@ti.com>
Message-ID: <1161dc3b-c889-c5d7-f7c8-baf5b7b79505@ti.com>
Date:   Thu, 1 Apr 2021 13:57:49 +0530
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On 3/29/21 11:52 PM, Pratyush Yadav wrote:
>>> +  cdns,fifo-depth:
>>> +    description:
>>> +      Size of the data FIFO in words.
>>> +    $ref: "/schemas/types.yaml#/definitions/uint32"
>>> +    enum: [ 128, 256 ]
>>> +    default: 128
>>> +
>>> +  cdns,fifo-width:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    description:
>>> +      Bus width of the data FIFO in bytes.
>>> +    default: 4
>> I assume there's some constraints on this?
> IIUC this is a matter of how the peripheral is implemented and there are 
> no clear constraints. Different implementations can use different bus 
> widths for the SRAM bus but I don't see any mention of minimum or 
> maximum values. FWIW, all users in the kernel use a 4 byte bus.
> 

IMO a safe constraint would be to set a range of 1 to 4 (8/16/24/32 bit
wide) given this represents SRAM bus width. Binding can always be
updated if there exists an implementation with higher SRAM bus
width/fifo-width (although that's highly unlikely given there are no
such examples today).

But leaving it open ended with range of 0 to UINT_MAX sounds incorrect
to me.

>> With that,
>>
>> Reviewed-by: Rob Herring <robh@kernel.org>
> Thanks.
>