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Date:   Thu, 1 Apr 2021 17:19:40 +0200
From:   Clemens Gruber <clemens.gruber@pqgruber.com>
To:     Thierry Reding <thierry.reding@gmail.com>
Cc:     Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= 
        <u.kleine-koenig@pengutronix.de>, linux-pwm@vger.kernel.org,
        Sven Van Asbroeck <TheSven73@gmail.com>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 4/7] pwm: pca9685: Support staggered output ON times
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On Thu, Apr 01, 2021 at 03:47:26PM +0200, Thierry Reding wrote:
> On Thu, Apr 01, 2021 at 09:50:44AM +0200, Clemens Gruber wrote:
> > Hi Thierry,
> > 
> > On Wed, Mar 31, 2021 at 06:21:32PM +0200, Thierry Reding wrote:
> > > On Wed, Mar 31, 2021 at 02:26:14PM +0200, Clemens Gruber wrote:
> > > > On Mon, Mar 29, 2021 at 08:02:06PM +0200, Uwe Kleine-K?nig wrote:
> > > > > On Mon, Mar 29, 2021 at 07:16:38PM +0200, Clemens Gruber wrote:
> > > > > > On Mon, Mar 29, 2021 at 07:03:57PM +0200, Uwe Kleine-K?nig wrote:
> > > > > > > On Mon, Mar 29, 2021 at 02:57:04PM +0200, Clemens Gruber wrote:
> > > > > > > > The PCA9685 supports staggered LED output ON times to minimize current
> > > > > > > > surges and reduce EMI.
> > > > > > > > When this new option is enabled, the ON times of each channel are
> > > > > > > > delayed by channel number x counter range / 16, which avoids asserting
> > > > > > > > all enabled outputs at the same counter value while still maintaining
> > > > > > > > the configured duty cycle of each output.
> > > > > > > > 
> > > > > > > > Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
> > > > > > > 
> > > > > > > Is there a reason to not want this staggered output? If it never hurts I
> > > > > > > suggest to always stagger and drop the dt property.
> > > > > > 
> > > > > > There might be applications where you want multiple outputs to assert at
> > > > > > the same time / to be synchronized.
> > > > > > With staggered outputs mode always enabled, this would no longer be
> > > > > > possible as they are spread out according to their channel number.
> > > > > > 
> > > > > > Not sure how often that usecase is required, but just enforcing the
> > > > > > staggered mode by default sounds risky to me.
> > > > > 
> > > > > There is no such guarantee in the PWM framework, so I don't think we
> > > > > need to fear breaking setups. Thierry?
> > > > 
> > > > Still, someone might rely on it? But let's wait for Thierry's opinion.
> > > 
> > > There's currently no way to synchronize two PWM channels in the PWM
> > > framework. And given that each PWM channel is handled separately the
> > > programming for two channels will never happen atomically or even
> > > concurrently, so I don't see how you could run two PWMs completely
> > > synchronized to one another.
> > 
> > As the PCA9685 has only one prescaler and one counter per chip, by
> > default, all PWMs enabled will go high at the same time. If they also
> > have the same duty cycle configured, they also go low at the same time.
> 
> What happens if you enable one of them, it then goes high and then you
> enable the next one? Is the second one going to get enabled on the next
> period? Or will it start in the middle of the period?

The channel configuration is updated at the end of the low cycle of the
channel in question and if the counter is already past the ON time, it
will start with the next period. So the second one should never start
while the first one is high (unless staggering mode is enabled).

> To truly enable them atomically, you'd have to ensure they all get
> enabled in basically the same write, right? Because otherwise you can
> still end up with just a subset enabled and the rest getting enabled
> only after the first period.

Yes. This could probably be achieved with auto-increment for consecutive
channels or with the special ALL channel for all channels.

In our usecases this is not required. I'd still like to send a follow up
patch in the future that at least implements the register writes per
channel with auto increment to not have intermediate states (due to high
and low byte being written separately)

> > > Or did I misunderstand and it's only the start time of the rising edge
> > > that's shifted, but the signal will remain high for a full duty cycle
> > > after that and then go down and remain low for period - duty - offset?
> > 
> > Yes, that's how it works.
> 
> That's less problematic because the signal will remain a standard PWM,
> it's just shifted by some amount. Technically pwm_apply_state() must
> only return when the signal has been enabled, so very strictly speaking
> you'd have to wait for a given amount of time to ensure that's correct.
> But again, I doubt that any use-case would require you to be that
> deterministic.

Yes, probably not and if we make it opt-in, it shouldn't be a problem.

> 
> > > That's slightly better than the above in that it likely won't trip up
> > > any consumers. But it might still be worth to make this configurable per
> > > PWM (perhaps by specifying a third specifier cell, in addition to the
> > > period and flags, that defines the offset/phase of the signal).
> > > 
> > > In both cases, doing this on a per-PWM basis will allow the consumer to
> > > specify that they're okay with staggered mode and you won't actually
> > > force it onto anyone. This effectively makes this opt-in and there will
> > > be no change for existing consumers.
> > 
> > I agree that it should be opt-in, but I am not sure about doing it
> > per-pwm:
> > The reason why you'd want staggered mode is to reduce EMI or current
> > spikes and it is most effective if it is enabled for all PWMs.
> > 
> > If it is specified in the DT anyway and you have a consumer that does
> > not support staggered mode (probably rare but can happen), then I'd
> > suggest just disabling it globally by not specifying nxp,staggered-mode;
> > 
> > Also it would make the configuration more complicated: You have to do
> > the "staggering" yourself and assign offsets per channel.
> > It's certainly easier to just enable or disable it.
> > 
> > What do you think?
> 
> Yeah, if you use an offset in the PWM specifier, users would have to
> manually specify the offset. An interesting "feature" of that would be
> that they could configure a subset of PWM channels to run synchronized
> (module the atomicity problems discussed above). Not sure if that's
> something anyone would ever want to do.

Yes and for the common case where you don't care it would be more work
for the user.

> 
> Another option would be to add some new flag that specifies that a given
> PWM channel may use this mode. In that case users wouldn't have to care
> about specifying the exact offset and instead just use the flag and rely
> on the driver to pick some offset. Within the driver you could then just
> keep the same computation that offsets by channel index, or you could
> have any other mechanism that you want.

OK, so maybe a PWM_STAGGERING_ALLOWED flag in dt-bindings/pwm/pwm.h,
pass it through via a new bool staggering_allowed in struct pwm_args?

Thanks,
Clemens