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From:   "Sit, Michael Wei Hong" <michael.wei.hong.sit@intel.com>
To:     Andrew Lunn <andrew@lunn.ch>
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Subject: RE: [PATCH net-next v2 0/2] Enable 2.5Gbps speed for stmmac
Thread-Topic: [PATCH net-next v2 0/2] Enable 2.5Gbps speed for stmmac
Thread-Index: AQHXKh1iSqorLH9tdkSQSbVyiN9Uw6ql+JIA
Date:   Mon, 5 Apr 2021 14:23:20 +0000
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> -----Original Message-----
> From: Andrew Lunn <andrew@lunn.ch>
> Sent: Monday, 5 April, 2021 9:11 PM
> To: Sit, Michael Wei Hong <michael.wei.hong.sit@intel.com>
> Cc: peppe.cavallaro@st.com; alexandre.torgue@st.com;
> joabreu@synopsys.com; davem@davemloft.net;
> kuba@kernel.org; mcoquelin.stm32@gmail.com;
> linux@armlinux.org.uk; Voon, Weifeng
> <weifeng.voon@intel.com>; Ong, Boon Leong
> <boon.leong.ong@intel.com>; qiangqing.zhang@nxp.com; Wong,
> Vee Khee <vee.khee.wong@intel.com>; fugang.duan@nxp.com;
> Chuah, Kim Tatt <kim.tatt.chuah@intel.com>;
> netdev@vger.kernel.org; linux-stm32@st-md-
> mailman.stormreply.com; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; hkallweit1@gmail.com
> Subject: Re: [PATCH net-next v2 0/2] Enable 2.5Gbps speed for
> stmmac
>=20
> On Mon, Apr 05, 2021 at 07:29:51PM +0800, Michael Sit Wei Hong
> wrote:
> > This patchset enables 2.5Gbps speed mode for stmmac.
> > Link speed mode is detected and configured at serdes power
> up sequence.
> > For 2.5G, we do not use SGMII in-band AN, we check the link
> speed mode
> > in the serdes and disable the in-band AN accordingly.
> >
> > Changes:
> > v1 -> v2
> >  patch 1/2
> >  -Remove MAC supported link speed masking
> >
> >  patch 2/2
> >  -Add supported link speed masking in the PCS
>=20
> So there still some confusion here.
>=20
> ------------            --------
> |MAC - PCS |---serdes---| PHY  |--- copper
> ------------            --------
>=20
>=20
> You have a MAC and an PCS in the stmmac IP block. That then has
> some
> sort of SERDES interface, running 1000BaseX, SGMII, SGMII
> overclocked
> at 2.5G or 25000BaseX. Connected to the SERDES you have a PHY
> which
> converts to copper, giving you 2500BaseT.
>=20
> You said earlier, that the PHY can only do 2500BaseT. So it should
> be
> the PHY driver which sets supported to 2500BaseT and no other
> speeds.
>=20
> You should think about when somebody uses this MAC with a
> different
> PHY, one that can do the full range of 10/half through to 2.5G
> full. What generally happens is that the PHY performs auto-neg to
> determine the link speed. For 10M-1G speeds the PHY will
> configure its
> SERDES interface to SGMII and phylink will ask the PCS to also be
> configured to SGMII. If the PHY negotiates 2500BaseT, it will
> configure its side of the SERDES to 2500BaseX or SGMII
> overclocked at
> 2.5G. Again, phylink will ask the PCS to match what the PHY is
> doing.
>=20
> So, where exactly is the limitation in your hardware? PCS or PHY?
The limitation in the hardware is at the PCS side where it is either runnin=
g
in SGMII 2.5G or SGMII 1G speeds.
When running on SGMII 2.5G speeds, we disable the in-band AN and use 2.5G s=
peed only
>=20
>      Andrew