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Tue, 6 Apr 2021 01:02:06 +0000 From: "Tian, Kevin" To: Jason Gunthorpe CC: "Liu, Yi L" , Jacob Pan , Jean-Philippe Brucker , LKML , Joerg Roedel , Lu Baolu , David Woodhouse , "iommu@lists.linux-foundation.org" , "cgroups@vger.kernel.org" , Tejun Heo , Li Zefan , Johannes Weiner , "Jean-Philippe Brucker" , Alex Williamson , Eric Auger , "Jonathan Corbet" , "Raj, Ashok" , "Wu, Hao" , "Jiang, Dave" Subject: RE: [PATCH V4 05/18] iommu/ioasid: Redefine IOASID set and allocation APIs Thread-Topic: [PATCH V4 05/18] iommu/ioasid: Redefine IOASID set and allocation APIs Thread-Index: AQHXDZub0CDG82VGXUmLEYgvMuPs4KqKkLIAgACg94CAAC72gIAAD04AgAADogCAAErUgIAETQEAgAOaswCAB7C3gIAAhxQwgADYDACAATCSAIAAVGMAgAELsQCAAHeZAIAAF3gAgAABVICAAAfXAIAAANyAgAEpdBCABcWUAIAAEDLQ Date: Tue, 6 Apr 2021 01:02:05 +0000 Message-ID: References: <20210330132830.GO2356281@nvidia.com> <20210331124038.GE1463678@nvidia.com> <20210401114648.GX1463678@nvidia.com> <20210401131533.GD1463678@nvidia.com> <20210401134641.GG1463678@nvidia.com> <20210405233946.GE7405@nvidia.com> In-Reply-To: <20210405233946.GE7405@nvidia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: nvidia.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR11MB1886.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1469b6f9-a43f-44bf-4d28-08d8f89798d6 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Apr 2021 01:02:05.9907 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: zAUviVwg0lJ922GQco0pypA1QXpBMrGnPi397iHgGSJYrA6SEIwDXvDXKSg/yHJsPc123j9EYC7srAMvSSAzuA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR11MB4932 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Jason Gunthorpe > Sent: Tuesday, April 6, 2021 7:40 AM >=20 > On Fri, Apr 02, 2021 at 07:58:02AM +0000, Tian, Kevin wrote: > > > From: Jason Gunthorpe > > > Sent: Thursday, April 1, 2021 9:47 PM > > > > > > On Thu, Apr 01, 2021 at 01:43:36PM +0000, Liu, Yi L wrote: > > > > > From: Jason Gunthorpe > > > > > Sent: Thursday, April 1, 2021 9:16 PM > > > > > > > > > > On Thu, Apr 01, 2021 at 01:10:48PM +0000, Liu, Yi L wrote: > > > > > > > From: Jason Gunthorpe > > > > > > > Sent: Thursday, April 1, 2021 7:47 PM > > > > > > [...] > > > > > > > I'm worried Intel views the only use of PASID in a guest is w= ith > > > > > > > ENQCMD, but that is not consistent with the industry. We need= to > see > > > > > > > normal nested PASID support with assigned PCI VFs. > > > > > > > > > > > > I'm not quire flow here. Intel also allows PASID usage in guest > without > > > > > > ENQCMD. e.g. Passthru a PF to guest, and use PASID on it withou= t > > > > > ENQCMD. > > > > > > > > > > Then you need all the parts, the hypervisor calls from the vIOMMU= , > and > > > > > you can't really use a vPASID. > > > > > > > > This is a diagram shows the vSVA setup. > > > > > > I'm not talking only about vSVA. Generic PASID support with arbitary > > > mappings. > > > > > > And how do you deal with the vPASID vs pPASID issue if the system has > > > a mix of physical devices and mdevs? > > > > > > > We plan to support two schemes. One is vPASID identity-mapped to > > pPASID then the mixed scenario just works, with the limitation of > > lacking of live migration support. The other is non-identity-mapped > > scheme, where live migration is supported but physical devices and > > mdevs should not be mixed in one VM if both expose SVA capability > > (requires some filtering check in Qemu). >=20 > That just becomes "block vPASID support if any device that > doesn't use ENQCMD is plugged into the guest" The limitation is only for physical device. and in reality it is not that bad. To support live migration with physical device we anyway need=20 additional work to migrate the device state (e.g. based on Max's work),=20 then it's not unreasonable to also mediate guest programming of=20 device specific PASID register to enable vPASID (need to translate in the whole VM lifespan but likely is not a hot path). >=20 > Which needs a special VFIO capability of some kind so qemu knows to > block it. This really needs to all be layed out together so someone > can understand it :( Or could simply based on whether the VFIO device supports live migration. >=20 > Why doesn't the siov cookbook explaining this stuff?? >=20 > > We hope the /dev/ioasid can support both schemes, with the minimal > > requirement of allowing userspace to tag a vPASID to a pPASID and > > allowing mdev to translate vPASID into pPASID, i.e. not assuming that > > the guest will always use pPASID. >=20 > What I'm a unclear of is if /dev/ioasid even needs to care about > vPASID or if vPASID is just a hidden artifact of the KVM connection to > setup the translation table and the vIOMMU driver in qemu. Not just for KVM. Also required by mdev, which needs to translate vPASID into pPASID when ENQCMD is not used. As I replied in another mail, possibly we don't need /dev/ioasid to know this fact, which=20 should only care about the operations related to pPASID. VFIO could carry vPASID information to mdev. KVM should have its own interface to know this information, as you suggested earlier. Thanks Kevin