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Date:   Tue, 06 Apr 2021 15:51:52 +0900
From:   Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To:     Rob Herring <robh+dt@kernel.org>, Arnd Bergmann <arnd@arndb.de>
Subject: Re: [PATCH 1/2] ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins for RTL8211E
Cc:     Masami Hiramatsu <masami.hiramatsu@linaro.org>,
        Jassi Brar <jaswinder.singh@linaro.org>,
        <devicetree@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>
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References: <1615250236-11349-1-git-send-email-hayashi.kunihiko@socionext.com>
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Gentle Ping.
Are there any comments about these two patches?

Thank you,

On Tue, 9 Mar 2021 09:37:15 +0900
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> wrote:

> After applying the commit bbc4d71d6354
> ("net: phy: realtek: fix rtl8211e rx/tx delay config"), the configuration
> register for TXDLY and RXDLY is set correctly.
> 
> Although PXs2 boards have RTL8211E for gigabit network PHY, it turrned out
> that the phy-mode should be RGMII-ID mode. This changes 'phy-mode' property
> to 'rgmii-id' as default.
> 
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
>  arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
> index 4d9f69a..5ba831e 100644
> --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
> +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
> @@ -583,7 +583,7 @@
>  			clocks = <&sys_clk 6>;
>  			reset-names = "ether";
>  			resets = <&sys_rst 6>;
> -			phy-mode = "rgmii";
> +			phy-mode = "rgmii-id";
>  			local-mac-address = [00 00 00 00 00 00];
>  			socionext,syscon-phy-mode = <&soc_glue 0>;
>  
> -- 
> 2.7.4

---
Best Regards,
Kunihiko Hayashi