Received: by 2002:a05:6a10:9848:0:0:0:0 with SMTP id x8csp4177858pxf; Tue, 6 Apr 2021 09:40:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwJj5hcRexD9jqjilRW4ndzmpOLq1uamT8N0uS0TGu2HLNBUUPHuAQVocv4Vi/VohMxLdck X-Received: by 2002:aa7:c694:: with SMTP id n20mr1474802edq.51.1617727231361; Tue, 06 Apr 2021 09:40:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617727231; cv=none; d=google.com; s=arc-20160816; b=UMk/F8rIkDXcLA5feA+8LnGYYe3qh/+wRIhsRr13Lt0xZLMPcr2tQK5ErVvNyVxEPk 91W7Xb9a4EwSn6XmCpq6m9q9vvVCDksG2oTSrb7F8BQZYylupmTKuPrLEYsJZfHhX6+T 1k8OhvUrbvbjlV9S3uFuHAzNoTIh2NFq5E9doRqa5VSoRnrn7us+3n0a4S9Bb1YmvI03 EGmzPP/QSg/XSJBJJRc9J68mnXL/V5QC5ACLnWL6Z9RDPbjmD6Ak2qvLyhWdULTcX6oW HG54CkNJvrSmj52NUY3f7MTGoecUiQj/u+rm0QXisIErc/Vmd8GWFB5/TwMpiaOWrRDm 1RFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version; bh=kyM/uX3bNRVEEpQyWz+heQsyz9AuEXH5GY8XvmdJ2M8=; b=b1UEzvvLFIASmChTwErYmMw6arnTD6lywdyeSppz1aHluV4GSx7bfN3quCfyBDYC2I PNqkQnEcTJh71LleD/19QcA4DDWZ3Ib8XccymrBXUWJZM6yD7t4d8img9pONFMdTQxyg fE13WUm1GvlG2vcj7ug0B1gZrm2+ZTFCfO6q/6PpCxSLZNckw8bVX8HkED1G4gDQmtuT xMh9GJoQKjj7WgcQeUaAJmzNC6Un+6G1te//MxO9hzXv1Q0CFmJAWhKsWrYM4NS1TXlm kzHempV8CEXMEp/ggXxS0MgHj0Vm/pyWWgh05BhjmEaRWwB2pSeytpchICn4dI+X2BDl uD/A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id f7si16059231edu.503.2021.04.06.09.40.07; Tue, 06 Apr 2021 09:40:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233768AbhDFH3X (ORCPT + 99 others); Tue, 6 Apr 2021 03:29:23 -0400 Received: from mail-vs1-f41.google.com ([209.85.217.41]:45901 "EHLO mail-vs1-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233687AbhDFH3W (ORCPT ); Tue, 6 Apr 2021 03:29:22 -0400 Received: by mail-vs1-f41.google.com with SMTP id u29so7255286vsi.12 for ; Tue, 06 Apr 2021 00:29:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=kyM/uX3bNRVEEpQyWz+heQsyz9AuEXH5GY8XvmdJ2M8=; b=W+4Aa6QzOWcKAq6imHFeSNF00ZGOAcXY03nxU1xpi6j+IJmdJMBo8Lu4mjURBUj+ns 6CdZ4Piy3BXuSMsSobpSEzeEKuOLec8ySVWKBltS5bNNYexsu26b2AJCvl9Fu+BTA1IJ Uw07bINTVjXnNnHVdgd92DTi3tSyCKlpHxddbp+BprQIV+vhm0fWKtB61g2PhYhsdDXb fDgBX8z9KTdRZEmcf0MT0Kyj/hn/2KvX5x6rB9c6RVmD/CPU+qaBCb2Qt5/okw5j3rjZ bWblQ1zcfTpf0Uawp/lEhgboitskm6RkGvtGHcLJSVRp9VcGuYtbmc9wbwLT5RmaQD7b HAQg== X-Gm-Message-State: AOAM533FKl8ghK06c7KDJGX/77ZnkTvCKyH7DTQXcb8vIji5C2mIOzzh PLSck5ibSzyZNAgKjQ0KVR6lO69vLUND0PuddzHAh3bQ X-Received: by 2002:a05:6102:3010:: with SMTP id s16mr12429339vsa.3.1617694154355; Tue, 06 Apr 2021 00:29:14 -0700 (PDT) MIME-Version: 1.0 References: <4fdaa113db089b8fb607f7dd818479f8cdcc4547.1617089871.git.fthain@telegraphics.com.au> In-Reply-To: <4fdaa113db089b8fb607f7dd818479f8cdcc4547.1617089871.git.fthain@telegraphics.com.au> From: Geert Uytterhoeven Date: Tue, 6 Apr 2021 09:29:03 +0200 Message-ID: Subject: Re: [PATCH] m68k: mvme147, mvme16x: Don't wipe PCC timer config bits To: Finn Thain Cc: Michael Pavone , linux-m68k , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 30, 2021 at 9:40 AM Finn Thain wrote: > Don't clear the timer 1 configuration bits when clearing the interrupt flag > and counter overflow. As Michael reported, "This results in no timer > interrupts being delivered after the first. Initialization then hangs > in calibrate_delay as the jiffies counter is not updated." > > On mvme16x, enable the timer after requesting the irq, consistent with > mvme147. > > Cc: Michael Pavone > Fixes: 7529b90d051e ("m68k: mvme147: Handle timer counter overflow") > Fixes: 19999a8b8782 ("m68k: mvme16x: Handle timer counter overflow") > Reported-and-tested-by: Michael Pavone > Signed-off-by: Finn Thain Thanks, applying, and queueing in the m68k for-v5.13 branch. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds