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In-Reply-To: <dd303c4c-713f-c68c-879d-f4212cc305ee@ghiti.fr>
From:   Vitaly Wool <vitaly.wool@konsulko.com>
Date:   Wed, 7 Apr 2021 10:38:05 +0200
Message-ID: <CAM4kBBLsWPVfL20Py=QVSUCT4QW6pDbJR_TVR=LtTVgMLqL1QQ@mail.gmail.com>
Subject: Re: [PATCH v6] RISC-V: enable XIP
To:     Alex Ghiti <alex@ghiti.fr>
Cc:     Palmer Dabbelt <palmerdabbelt@google.com>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Bin Meng <bin.meng@windriver.com>,
        Anup Patel <anup@brainfault.org>,
        Alistair Francis <Alistair.Francis@wdc.com>,
        Nicolas Pitre <nico@fluxnic.net>
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Hi Alex,

<snip>
> > All in all, I am quite sure now that your take on XIP is working fine.
> > The issue with single-core boot under QEmu seems to be  less
> > reproducible on slower machines running QEmu and more reproducible on
> > higher performance ones. It's not clear to me if that is a QEmu
> > problem or an in-kernel race, but it's hardly a XIP problem: I was
> > able to reproduce it once on a non-XIP kernel too, by copying it to
> > RAM in u-boot and giving it a 'go'.
>
> Ok then I'll post a v7 of your patch soon hoping it will go to for-next.
> I'll add my SoB to yours as I modified quite a few things and I thin
> people need to know who to yell at, if you don't mind of course.

No, absolutely not. :) Thanks for digging into this!

Best regards,
   Vitaly