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Date:   Wed, 7 Apr 2021 17:40:47 +0200
From:   Peter Zijlstra <peterz@infradead.org>
To:     Like Xu <like.xu@linux.intel.com>
Cc:     Sean Christopherson <seanjc@google.com>,
        Paolo Bonzini <pbonzini@redhat.com>, eranian@google.com,
        andi@firstfloor.org, kan.liang@linux.intel.com,
        wei.w.wang@intel.com, Wanpeng Li <wanpengli@tencent.com>,
        Vitaly Kuznetsov <vkuznets@redhat.com>,
        Jim Mattson <jmattson@google.com>,
        Joerg Roedel <joro@8bytes.org>, kvm@vger.kernel.org,
        x86@kernel.org, linux-kernel@vger.kernel.org,
        Luwei Kang <luwei.kang@intel.com>
Subject: Re: [PATCH v4 09/16] KVM: x86/pmu: Add PEBS_DATA_CFG MSR emulation
 to support adaptive PEBS
Message-ID: <YG3Sfy2T8tjqSgkp@hirez.programming.kicks-ass.net>
References: <20210329054137.120994-1-like.xu@linux.intel.com>
 <20210329054137.120994-10-like.xu@linux.intel.com>
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On Mon, Mar 29, 2021 at 01:41:30PM +0800, Like Xu wrote:
> @@ -3863,6 +3864,12 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
>  		arr[2].host = (unsigned long)ds;
>  		arr[2].guest = pmu->ds_area;

		*nr = 3;
>  
> +		if (baseline) {
> +			arr[3].msr = MSR_PEBS_DATA_CFG;
> +			arr[3].host = cpuc->pebs_data_cfg;
> +			arr[3].guest = pmu->pebs_data_cfg;

			*nr = 4;
> +		}
> +
>  		/*
>  		 * If PMU counter has PEBS enabled it is not enough to
>  		 * disable counter on a guest entry since PEBS memory
> @@ -3879,9 +3886,11 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
>  		else {
>  			arr[1].guest = arr[1].host;
>  			arr[2].guest = arr[2].host;
> +			if (baseline)
> +				arr[3].guest = arr[3].host;
>  		}
>  
> -		*nr = 3;
> +		*nr = baseline ? 4 : 3;

And you don't need yet another branch to determine a value you already
know.

>  	}