Subject: Re: Can context switches be faster?
From: Arjan van de Ven <arjan@infradead.org>
To: John Richard Moser <nigelenki@comcast.net>
Cc: linux-kernel@vger.kernel.org
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Organization: Intel International BV
Date: Thu, 12 Oct 2006 20:37:11 +0200
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On Thu, 2006-10-12 at 14:25 -0400, John Richard Moser wrote:

Hi,

> So apparently most CPUs virtually address L1 cache and physically
> address L2; but sometimes physically addressing L1 is better.. hur.

if you are interested in this I would strongly urge you to read Curt
Schimmel's book (UNIX(R) Systems for Modern Architectures: Symmetric
Multiprocessing and Caching for Kernel Programmers); it explains this
and related materials really really well.


>   - Does the current code act on these behaviors, or just flush all
>     cache regardless?

the cache flushing is a per architecture property. On x86, the cache
flushing isn't needed; but a TLB flush is. Depending on your hardware
that can be expensive as well. 

Greetings,
    Arjan van de Ven

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