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Date:   Thu, 08 Apr 2021 21:33:15 -0400
Message-Id: <CAIT0Y0W41EH.11ZSYT40VQAP6@shaak>
Cc:     <mturquette@baylibre.com>, <sboyd@kernel.org>,
        <linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <devicetree@vger.kernel.org>
Subject: Re: [PATCH v4 3/3] dt-bindings: clock: add ti,lmk04832 bindings
From:   "Liam Beguin" <liambeguin@gmail.com>
To:     "Rob Herring" <robh@kernel.org>
References: <20210407005330.2890430-1-liambeguin@gmail.com>
 <20210407005330.2890430-4-liambeguin@gmail.com>
 <20210408201333.GA1882021@robh.at.kernel.org>
In-Reply-To: <20210408201333.GA1882021@robh.at.kernel.org>
Precedence: bulk

On Thu Apr 8, 2021 at 4:13 PM EDT, Rob Herring wrote:
> On Tue, Apr 06, 2021 at 08:53:30PM -0400, Liam Beguin wrote:
> > From: Liam Beguin <lvb@xiphos.com>
> >=20
> > Document devicetree bindings for Texas Instruments' LMK04832.
> > The LMK04208 is a high performance clock conditioner with superior cloc=
k
> > jitter cleaning, generation, and distribution with JEDEC JESD204B
> > support.
> >=20
> > Signed-off-by: Liam Beguin <lvb@xiphos.com>
> > ---
> >  .../bindings/clock/ti,lmk04832.yaml           | 209 ++++++++++++++++++
> >  1 file changed, 209 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/ti,lmk04832=
.yaml
> >=20
> > diff --git a/Documentation/devicetree/bindings/clock/ti,lmk04832.yaml b=
/Documentation/devicetree/bindings/clock/ti,lmk04832.yaml
> > new file mode 100644
> > index 000000000000..a9f8b9b720fc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/ti,lmk04832.yaml
> > @@ -0,0 +1,209 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Clock bindings for the Texas Instruments LMK04832
> > +
> > +maintainers:
> > +  - Liam Beguin <liambeguin@gmail.com>
> > +
> > +description: |
> > +  Devicetree binding for the LMK04832, a clock conditioner with JEDEC =
JESD204B
> > +  support. The LMK04832 is pin compatible with the LMK0482x family.
> > +
> > +  Link to datasheet, https://www.ti.com/lit/ds/symlink/lmk04832.pdf
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - ti,lmk04832
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  '#address-cells':
> > +    const: 1
> > +
> > +  '#size-cells':
> > +    const: 0
> > +
> > +  '#clock-cells':
> > +    const: 1
> > +
> > +  spi-max-frequency:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description:
> > +      Maximum SPI clocking speed of the device in Hz.
>
> Already has a type and description, just need:
>
> spi-max-frequency: true
>
> (Or a range of values if you know the maximum).
>
> > +
> > +  clocks:
> > +    items:
> > +      - description: PLL2 reference clock.
> > +
> > +  clock-names:
> > +    items:
> > +      - const: oscin
> > +
> > +  reset-gpios:
> > +    maxItems: 1
> > +
> > +  ti,spi-4wire-rdbk:
> > +    description: |
> > +      Select SPI 4wire readback pin configuration.
> > +      Available readback pins are,
> > +        CLKin_SEL0 0
> > +        CLKin_SEL1 1
> > +        RESET 2
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [0, 1, 2]
> > +    default: 1
> > +
> > +  ti,vco-hz:
> > +    description: Optional to set VCO frequency of the PLL in Hertz.
> > +
> > +  ti,sysref-ddly:
> > +    description: SYSREF digital delay value.
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    minimum: 8
> > +    maximum: 8191
> > +    default: 8
> > +
> > +  ti,sysref-mux:
> > +    description: |
> > +      SYSREF Mux configuration.
> > +      Available options are,
> > +        Normal SYNC 0
> > +        Re-clocked 1
> > +        SYSREF Pulser 2
> > +        SYSREF Continuous 3
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [0, 1, 2, 3]
> > +    default: 3
> > +
> > +  ti,sync-mode:
> > +    description: SYNC pin configuration.
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [0, 1, 2]
> > +    default: 1
> > +
> > +  ti,sysref-pulse-count:
> > +    description:
> > +      Number of SYSREF pulses to send when SYSREF is not in continuous=
 mode.
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [1, 2, 4, 8]
> > +    default: 4
> > +
> > +patternProperties:
> > +  "@[0-9a-d]+$":
> > +    type: object
> > +    description:
> > +      Child nodes used to configure output clocks.
> > +
> > +    properties:
> > +      reg:
> > +        description:
> > +          clock output identifier.
> > +        minimum: 0
> > +        maximum: 13
> > +
> > +      ti,clkout-fmt:
> > +        description:
> > +          Clock output format.
> > +          Available options are,
> > +            Powerdown 0x00
> > +            LVDS 0x01
> > +            HSDS 6 mA 0x02
> > +            HSDS 8 mA 0x03
> > +            LVPECL 1600 mV 0x04
> > +            LVPECL 2000 mV 0x05
> > +            LCPECL 0x06
> > +            CML 16 mA 0x07
> > +            CML 24 mA 0x08
> > +            CML 32 mA 0x09
> > +            CMOS (Off/Inverted) 0x0a
> > +            CMOS (Normal/Off) 0x0b
> > +            CMOS (Inverted/Inverted) 0x0c
> > +            CMOS (Inverted/Normal) 0x0d
> > +            CMOS (Normal/Inverted) 0x0e
> > +            CMOS (Normal/Normal) 0x0f
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        minimum: 0
> > +        maximum: 15
> > +
> > +      ti,clkout-sysref:
> > +        description:
> > +          Select SYSREF clock path for output clock.
> > +        type: boolean
> > +
> > +    required:
> > +      - reg
>
> additionalProperties: false
>

Apologies for double posting.
I just realized this is for the child node. Will fix.

Thanks,
Liam

> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - '#clock-cells'
> > +  - clocks
> > +  - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    clocks {
> > +        lmk04832_oscin: oscin {
> > +            compatible =3D "fixed-clock";
> > +
> > +            #clock-cells =3D <0>;
> > +            clock-frequency =3D <122880000>;
> > +            clock-output-names =3D "lmk04832-oscin";
> > +        };
> > +    };
> > +
> > +    spi0 {
> > +        #address-cells =3D <1>;
> > +        #size-cells =3D <0>;
> > +
> > +        lmk04832: clock-controller@0 {
> > +            #address-cells =3D <1>;
> > +            #size-cells =3D <0>;
> > +
> > +            reg =3D <0>;
> > +
> > +            compatible =3D "ti,lmk04832";
> > +            spi-max-frequency =3D <781250>;
> > +
> > +            reset-gpios =3D <&gpio_lmk 0 0 0>;
> > +
> > +            #clock-cells =3D <1>;
> > +            clocks =3D <&lmk04832_oscin>;
> > +            clock-names =3D "oscin";
> > +
> > +            ti,spi-4wire-rdbk =3D <0>;
> > +            ti,vco-hz =3D <2457600000>;
> > +
> > +            assigned-clocks =3D
> > +                <&lmk04832 0>, <&lmk04832 1>,
> > +                <&lmk04832 2>, <&lmk04832 3>,
> > +                <&lmk04832 4>,
> > +                <&lmk04832 6>, <&lmk04832 7>,
> > +                <&lmk04832 10>, <&lmk04832 11>;
> > +            assigned-clock-rates =3D
> > +                <122880000>, <384000>,
> > +                <122880000>, <384000>,
> > +                <122880000>,
> > +                <153600000>, <384000>,
> > +                <614400000>, <384000>;
> > +
> > +            clkout0@0 {
> > +                reg =3D <0>;
> > +                ti,clkout-fmt =3D <0x01>; // LVDS
> > +            };
> > +
> > +            clkout1@1 {
> > +                reg =3D <1>;
> > +                ti,clkout-fmt =3D <0x01>; // LVDS
> > +                ti,clkout-sysref;
> > +            };
> > +        };
> > +    };
> > --=20
> > 2.30.1.489.g328c10930387
> >=20