Received: by 2002:a05:6a10:9848:0:0:0:0 with SMTP id x8csp1018005pxf; Thu, 8 Apr 2021 20:08:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxpdkCaQjA1pu5leXhNp+fQwAba17w3JwUp737fhsgYyRot5tkYS61UHmPWYyJHf1CBqLvZ X-Received: by 2002:a17:90a:1f49:: with SMTP id y9mr12143649pjy.69.1617937710327; Thu, 08 Apr 2021 20:08:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617937710; cv=none; d=google.com; s=arc-20160816; b=ipuS9fOYWq9o2PVMpZ341FiYX942mnbpqxav2CsdoOJfuGpCjDbu/RKiUlNcLcH5TS ob9LAgb1H1Az07wWbe+nEXgwhNpVE16LQI82yap1+4ihLHfcOTZzbpigcbD+gZFFPcpH Mjh8jkW6l9iv7KuzAfphnf1DguB66hGPN3xny3sbKfxuMnajk7YTlHAHhnSKk9UeXZjI QW3xveppWfj22JqXoe+2CqHZrlvVP0iT+dUCkN9GfngH4KszuxNUoNIWqf8BNybJ4wJS blLND3OTk1crBVCHjDluDR3gGe53MqdpqF136dn7X9EDMp4I5nrc5nJqNtCiknz2bWs1 3ikw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=uy/LJqbcD1LX26ZJT7guMFWEDzAVu1jrHNQLGhfeBvU=; b=tCFeY13Ei89ybtRCJ5iZqQq6VF1h1YPE388BPlIBwUzI9Ypm0rHA4rC1tGd7k9mYU/ 4szUyBzJ8tDIHtlPU1NsIn5jh9cb5a8lAv45vnM6g6z6evskwqwq4vUpHbupiZaxoUJl 78Juh5GxUb/aNFmhh86DaGiv4QlRpcN+CAfT5zHs5Erg9NQrUqxA38/iSk6spHsJeEyg D0oox1bSCci9N5JAKpZglVDJ1db36jm/6oV5Fj9YhQa4gcfBxwuXh1frJ6OEqE0+SRYD 0BCz6VOG2q9Ql37VV3iDfpvU11Xd38aucneTpxuqApPqGAGqcx6NyaanHh2XSoDBogIU elcg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q5si1310953pls.67.2021.04.08.20.08.17; Thu, 08 Apr 2021 20:08:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233025AbhDIDHc (ORCPT + 99 others); Thu, 8 Apr 2021 23:07:32 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:47824 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232662AbhDIDHc (ORCPT ); Thu, 8 Apr 2021 23:07:32 -0400 X-UUID: ac3f69d98a1645edb85bebfedd5c5576-20210409 X-UUID: ac3f69d98a1645edb85bebfedd5c5576-20210409 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 410952694; Fri, 09 Apr 2021 11:07:16 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 9 Apr 2021 11:07:12 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 9 Apr 2021 11:07:11 +0800 From: Chunfeng Yun To: Bjorn Andersson , Vinod Koul CC: Andy Gross , Kishon Vijay Abraham I , Matthias Brugger , , , , , Chunfeng Yun Subject: [PATCH] phy: qcom-qmp: remove redundant error of clock bulk Date: Fri, 9 Apr 2021 11:07:10 +0800 Message-ID: <1617937630-24832-1-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 32FA1E2DB58F90B2EEED82E4AD1BB02B3B0CEDA66E5DA65390E399B2F26CF9072000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is error log in clk_bulk_prepare/enable() Signed-off-by: Chunfeng Yun --- drivers/phy/qualcomm/phy-qcom-qmp.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 9cdebe7..f14b8be 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -3598,10 +3598,8 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) } ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); - if (ret) { - dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret); + if (ret) goto err_rst; - } if (cfg->has_phy_dp_com_ctrl) { qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, @@ -4035,10 +4033,8 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) } ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); - if (ret) { - dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret); + if (ret) return ret; - } ret = clk_prepare_enable(qphy->pipe_clk); if (ret) { -- 1.8.1.1.dirty