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[23.128.96.18]) by mx.google.com with ESMTP id t13si623693pfh.89.2021.04.09.01.23.57; Fri, 09 Apr 2021 01:24:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232795AbhDIIV4 (ORCPT + 99 others); Fri, 9 Apr 2021 04:21:56 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:55133 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232804AbhDIIVy (ORCPT ); Fri, 9 Apr 2021 04:21:54 -0400 X-UUID: 201b3f43cbf7468ab354bf92f2334ac9-20210409 X-UUID: 201b3f43cbf7468ab354bf92f2334ac9-20210409 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 963400162; Fri, 09 Apr 2021 16:21:39 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 9 Apr 2021 16:21:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 9 Apr 2021 16:21:37 +0800 From: Nina Wu To: Rob Herring , Matthias Brugger CC: Nina Wu , Zhen Lei , Neal Liu , , , , , , Subject: [PATCH v3 7/7] arm64: dts: mt8192: Add devapc node Date: Fri, 9 Apr 2021 16:19:37 +0800 Message-ID: <1617956377-4075-7-git-send-email-nina-cm.wu@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1617956377-4075-1-git-send-email-nina-cm.wu@mediatek.com> References: <1617956377-4075-1-git-send-email-nina-cm.wu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Nina Wu Add devapc nodes to mt8192. Signed-off-by: Nina Wu --- This patch depends on "Add dt-bindings of MT8192 clocks" [1] and "Add mt8192 clock controllers" [2] [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210324104110.13383-7-chun-jie.chen@mediatek.com/ [2] https://patchwork.kernel.org/project/linux-mediatek/patch/20210331083854.7650-2-chun-jie.chen@mediatek.com/ --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index fe24cc6..4f5fb62 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -518,6 +518,33 @@ clock-names = "clk13m"; }; + devapc_infra: devapc@10207000 { + compatible = "mediatek,mt8192-devapc"; + reg = <0 0x10207000 0 0x1000>; + vio-idx-num = <367>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_DEVICE_APC>; + clock-names = "devapc-infra-clock"; + }; + + devapc_peri: devapc@10274000 { + compatible = "mediatek,mt8192-devapc"; + reg = <0 0x10274000 0 0x1000>; + vio-idx-num = <292>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_DEVICE_APC>; + clock-names = "devapc-infra-clock"; + }; + + devapc_peri2: devapc@10275000 { + compatible = "mediatek,mt8192-devapc"; + reg = <0 0x10275000 0 0x1000>; + vio-idx-num = <242>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_DEVICE_APC>; + clock-names = "devapc-infra-clock"; + }; + scp_adsp: syscon@10720000 { compatible = "mediatek,mt8192-scp_adsp", "syscon"; reg = <0 0x10720000 0 0x1000>; @@ -662,6 +689,15 @@ status = "disabled"; }; + devapc_peri_par: devapc@11020000 { + compatible = "mediatek,mt8192-devapc"; + reg = <0 0x11020000 0 0x1000>; + vio-idx-num = <58>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_DEVICE_APC>; + clock-names = "devapc-infra-clock"; + }; + nor_flash: spi@11234000 { compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>; -- 2.6.4