Received: by 2002:a05:6a10:9848:0:0:0:0 with SMTP id x8csp1378877pxf; Fri, 9 Apr 2021 07:05:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzsR3ikYvZyASsnED+rMMRmJJ3YqB56bhyoz/FnPHmivGzmvadX2Gwmi+n5bYm3E9FVehYb X-Received: by 2002:a63:338e:: with SMTP id z136mr13354937pgz.115.1617977131660; Fri, 09 Apr 2021 07:05:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617977131; cv=none; d=google.com; s=arc-20160816; b=B2W4nOJeI/mBsuJsDRa9dwa5HsB7UHB9pt91/KntEq+rs3KLlXqVHb2HlVWxaXUgyx RVV54m7MH2B9er/8oGWw0fs/vQAx0mlotnE4+fnMpD3K4sQ/Rf4QVB20VuhZRsqZxD// xkXpMGY0tXJS6Or0fivculYoOAlAog/CegrIilR6IOwdPuDFKEptlL++gko/E1n8zbgY OylrCSZ9i91aAAJcao33sZooWvhjEtusMqgmzb2wnST2knsRhrNFpNW9A1IzQXybEKp1 QVmLnffmiECBOUFbnCfkHDGJIjszks4ISOXncRR0I0AnQobdyVtbVWtguuWlF3IGMypq Xm4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=ex9PdVb0AT6Mc3IAP4XyORuemlUBsdKRDjc3Cgm4Nr8=; b=tQ+OgYRqnyuicJfToJ+dd5DZiKzdaalOr7XCADf9bw/vqGDTNi5/yJBZiV/woSJjIB GuvxEu/0TvnB6cHRliB3xzNu1rUN7V7q3H7XuocfoOrgzEWMctRCY6388EYnMdFP0sb/ ZTr7BI5Dq/gJdcOVj7aI6JVW/iBEgjrzCG/5HrwMSfAxl1wYquVW1JkaYG+33Y9rLU0e KBLfnqbPv/eW//DP7UrPwDAFMAtO/ohMuDaRv6i0zDoHH9MPYPdSgKIUkf8fcTFuysyf T+0D6LtVtnhLS+fJWq4iCLSUCCbkzcf/RnqEI3QzxVGENJuMNux5wOP2D9ppxgj0xIhS vvBg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id d5si3019377pjv.118.2021.04.09.07.05.17; Fri, 09 Apr 2021 07:05:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233851AbhDIODY (ORCPT + 99 others); Fri, 9 Apr 2021 10:03:24 -0400 Received: from mail.kernel.org ([198.145.29.99]:50572 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232796AbhDIODX (ORCPT ); Fri, 9 Apr 2021 10:03:23 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 02B5B610F7; Fri, 9 Apr 2021 14:03:07 +0000 (UTC) Date: Fri, 9 Apr 2021 19:33:04 +0530 From: Manivannan Sadhasivam To: Alex Elder Cc: bjorn.andersson@linaro.org, agross@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] clk: qcom: rpmh: add support for SDX55 rpmh IPA clock Message-ID: <20210409140304.GF31856@work> References: <20210409134407.841137-1-elder@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210409134407.841137-1-elder@linaro.org> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 09, 2021 at 08:44:07AM -0500, Alex Elder wrote: > The IPA core clock is required for SDX55. Define it. > > Signed-off-by: Alex Elder I tested this patch on couple of SDX55 based boards like Telit FN980 and Thundercomm T55. Hence, Tested-by: Manivannan Sadhasivam Also cross checked the IPA clock definition using QC internal docs, so Reviewed-by: Manivannan Sadhasivam Thanks, Mani > --- > drivers/clk/qcom/clk-rpmh.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c > index c623ce9004063..552d1cbfea4c0 100644 > --- a/drivers/clk/qcom/clk-rpmh.c > +++ b/drivers/clk/qcom/clk-rpmh.c > @@ -380,6 +380,7 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = { > DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1); > DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1); > DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0"); > +DEFINE_CLK_RPMH_BCM(sdx55, ipa, "IP0"); > > static struct clk_hw *sdx55_rpmh_clocks[] = { > [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, > @@ -389,6 +390,7 @@ static struct clk_hw *sdx55_rpmh_clocks[] = { > [RPMH_RF_CLK2] = &sdx55_rf_clk2.hw, > [RPMH_RF_CLK2_A] = &sdx55_rf_clk2_ao.hw, > [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw, > + [RPMH_IPA_CLK] = &sdx55_ipa.hw, > }; > > static const struct clk_rpmh_desc clk_rpmh_sdx55 = { > -- > 2.27.0 >