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[23.128.96.18]) by mx.google.com with ESMTP id z26si2562821edx.5.2021.04.09.09.25.21; Fri, 09 Apr 2021 09:25:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233837AbhDIQWq (ORCPT + 99 others); Fri, 9 Apr 2021 12:22:46 -0400 Received: from mx.socionext.com ([202.248.49.38]:3595 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233657AbhDIQWo (ORCPT ); Fri, 9 Apr 2021 12:22:44 -0400 Received: from unknown (HELO iyokan2-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 10 Apr 2021 01:22:27 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan2-ex.css.socionext.com (Postfix) with ESMTP id 03E6B2059035; Sat, 10 Apr 2021 01:22:28 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Sat, 10 Apr 2021 01:22:27 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan2.css.socionext.com (Postfix) with ESMTP id 8D282B1D40; Sat, 10 Apr 2021 01:22:27 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Marc Zyngier Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jassi Brar , Masami Hiramatsu , Kunihiko Hayashi Subject: [PATCH v10 0/3] PCI: uniphier: Add PME/AER support for UniPhier PCIe host controller Date: Sat, 10 Apr 2021 01:22:15 +0900 Message-Id: <1617985338-19648-1-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds a new function called by MSI handler in DesignWare PCIe framework, that invokes PME and AER funcions to detect the factor from SoC-dependent registers. Changes since v9: - Fix the description of pcie_prot_service_get_irq() Changes since v8: - Add uniphier_pcie_host_init_complete() that finds PME/AER vIRQ number after calling dw_pcie_host_init() - Add conditions to depend on CONFIG_PCIE_PME and CONFIG_PCIEAER instead of CONFIG_PCIEPORTBUS - Add Acked-by: line to portdrv patch Changes since v7: - Add Reviewed-by: line to 1st and 3rd patches Changes since v6: - Separate patches for iATU and phy error from this series - Add Reviewed-by: line to dwc patch Changes since v5: - Add pcie_port_service_get_irq() function to pcie/portdrv - Call pcie_port_service_get_irq() to get vIRQ interrupt number for PME/AER - Rebase to the latest linux-next branch, and remove devm_platform_ioremap_resource_byname() replacement patch Changes since v4: - Add Acked-by: line to dwc patch Changes since v3: - Move msi_host_isr() call into dw_handle_msi_irq() - Move uniphier_pcie_misc_isr() call into the guard of chained_irq - Use a bool argument is_msi instead of pci_msi_enabled() - Consolidate handler calls for the same interrupt - Fix typos in commit messages Changes since v2: - Avoid printing phy error message in case of EPROBE_DEFER - Fix iATU register mapping method - dt-bindings: Add Acked-by: line - Fix typos in commit messages - Use devm_platform_ioremap_resource_byname() Changes since v1: - Add check if struct resource is NULL - Fix warning in the type of dev_err() argument Kunihiko Hayashi (3): PCI: portdrv: Add pcie_port_service_get_irq() function PCI: dwc: Add msi_host_isr() callback PCI: uniphier: Add misc interrupt handler to invoke PME and AER drivers/pci/controller/dwc/pcie-designware-host.c | 3 + drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-uniphier.c | 101 +++++++++++++++++++--- drivers/pci/pcie/portdrv.h | 1 + drivers/pci/pcie/portdrv_core.c | 16 ++++ 5 files changed, 110 insertions(+), 12 deletions(-) -- 2.7.4