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Subject: Re: [PATCH 4/4] ARM: dts: Fix-up EMMC2 controller's frequency
To:     Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
        Alan Cooper <alcooperx@gmail.com>,
        Florian Fainelli <f.fainelli@gmail.com>,
        Scott Branden <sbranden@broadcom.com>
Cc:     Nicolas Saenz Julienne <nsaenz@kernel.org>,
        "moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        linux-mmc <linux-mmc@vger.kernel.org>,
        DTML <devicetree@vger.kernel.org>,
        BCM Kernel Feedback <bcm-kernel-feedback-list@broadcom.com>,
        linux-rpi-kernel@lists.infradead.org, phil@raspberrypi.com,
        Tim Gover <tim.gover@raspberrypi.com>,
        Adrian Hunter <adrian.hunter@intel.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        Rob Herring <robh+dt@kernel.org>
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Message-ID: <6dfd1108-deaa-8606-01a9-4739e7c2da91@i2se.com>
Date:   Fri, 9 Apr 2021 20:28:59 +0200
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Hi Nicolas,

Am 09.04.21 um 12:54 schrieb Nicolas Saenz Julienne:
> Hi again,
>
> On Wed, 2021-04-07 at 16:37 -0400, Alan Cooper wrote:
>> Nicolas,
>>
>> I got a better description of the failure and it looks like the bus
>> clock needs to be limited to 300KHz for a 500MHz core clock.
>> What's happening is that an internal reset sequence is needed after a
>> command timeout and the reset signal needs to be asserted for at least
>> 2 ticks of the bus clock. This is done using a 12 bit counter clocked
>> by the core clock. That means a 500MHz core clock produces a 122KHz
>> reset signal which is too fast for 2 ticks of the 200KHz bus clock
>> (100KHz) but is okay for the 300KHz (150Khz) bus clock.
> Is there any value in implementing this in a generic way?

i don't have any idea which callback could manipulate the reset
duration. Limiting the min clk frequency looks like the less invasive
solution to me. Touching the DT isn't recommend.

Best regards