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[23.128.96.18]) by mx.google.com with ESMTP id u13si4964019pgf.212.2021.04.09.17.11.06; Fri, 09 Apr 2021 17:11:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kvqj5R9f; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235250AbhDJAJG (ORCPT + 99 others); Fri, 9 Apr 2021 20:09:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235224AbhDJAJG (ORCPT ); Fri, 9 Apr 2021 20:09:06 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C137C061762 for ; Fri, 9 Apr 2021 17:08:52 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id s17so8392931ljc.5 for ; Fri, 09 Apr 2021 17:08:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Ca+cCLqwiSnggzRSOZBhrhJV19U5tZ8nzn1LCCEhXdg=; b=Kvqj5R9fHJthTXbOIqCSzl9xTNI1UFi1KuTayaDFWynrwqGulsO7RSRfsivnOSW024 O7yaOvZ/MmF7FdGDCsQ/XRnQKYPRTb/QxUYkCGvd7nLGKUSvdPRJwaBSC+S0up3E3tAe xdh1rcfbbcBtbctQvrJ0nRYCVPF9jc8OkxxljiyvhSW15wHWGUlIe4nkFGH7zGdtfzNJ B+ZgNqomXtnR1uB4WzOf8JGbWdjLLAMfb78zVqpY1+8KTe7hL/Xpcjk2iAqzOD+gnsYe ldHXNsz1fbYzl1q2uj4WXFT9AznMeJ6OJIBLUOmTkzQNtMVZgqm1w+YcOlsRB97WNkpj uGnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Ca+cCLqwiSnggzRSOZBhrhJV19U5tZ8nzn1LCCEhXdg=; b=Q9w91lDBSKla4gYU5yBlF6gjggPX+4mqbpAunnemnpB2raoGn0rfEZaqu94H0PPXFW cFSKsp65EjebQC+FUvmy0pIC/2Ju6pBmyKV56DsRPnfN6xjdTIUhetIJvhkHKQxC84w4 6jonX4xNN0G1PpifyS3snc5PLVCCB4x8mE3A/oXjo01zUxqrbahztgdfwT/Bd4iDWBAj FE9DHFguh91dUxALgtpRm9iFAYm/nz5NEX7hJu2qQJBs2d51K2iwWqUU5eTPGnf47fo0 O9xVoV8QF22x5vEwG0iQkAX51Zw5onruqraTZzaV+AqEG+7k0V6LbV4xDoI9P31tVVQ8 +yrA== X-Gm-Message-State: AOAM533LJfiS2AvBmn14oIyGDJCatS5Osu51kdFtVry/1OeV3mMbHxxU tuTc+5W452bgSiWbhv7uG9XmHU0WH8sMc9rn8QQb/g== X-Received: by 2002:a2e:700a:: with SMTP id l10mr10716412ljc.368.1618013330856; Fri, 09 Apr 2021 17:08:50 -0700 (PDT) MIME-Version: 1.0 References: <20210409082522.625168-1-tudor.ambarus@microchip.com> In-Reply-To: <20210409082522.625168-1-tudor.ambarus@microchip.com> From: Linus Walleij Date: Sat, 10 Apr 2021 02:08:39 +0200 Message-ID: Subject: Re: [PATCH] pinctrl: at91-pio4: Fix slew rate disablement To: Tudor Ambarus Cc: Ludovic Desroches , Claudiu Beznea , Nicolas Ferre , Alexandre Belloni , Linux ARM , "open list:GPIO SUBSYSTEM" , linux-kernel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 9, 2021 at 10:25 AM Tudor Ambarus wrote: > The slew rate was enabled by default for each configuration of the > pin. In case the pin had more than one configuration, even if > we set the slew rate as disabled in the device tree, the next pin > configuration would set again the slew rate enabled by default, > overwriting the slew rate disablement. > Instead of enabling the slew rate by default for each pin configuration, > enable the slew rate by default just once per pin, regardless of the > number of configurations. This way the slew rate disablement will also > work for cases where pins have multiple configurations. > > Fixes: 440b144978ba ("pinctrl: at91-pio4: add support for slew-rate") > Signed-off-by: Tudor Ambarus Patch applied! Yours, Linus Walleij