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From:   Jiuyang Liu <liu@jiuyang.me>
To:     Palmer Dabbelt <palmer@dabbelt.com>
Cc:     alex@ghiti.fr, waterman@eecs.berkeley.edu,
        Paul Walmsley <paul.walmsley@sifive.com>,
        aou@eecs.berkeley.edu, akpm@linux-foundation.org,
        geert@linux-m68k.org, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] implement flush_cache_vmap and flush_cache_vunmap for RISC-V
Date:   Mon, 12 Apr 2021 00:13:32 +0000
Message-ID: <1846750.LAPMfGk2HC@nuc>
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References: <mhng-92e28f5c-ced0-4a92-949f-0fd865c0bbf5@palmerdabbelt-glaptop>
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On Sunday, April 11, 2021 9:41:07 PM UTC you wrote:
> On Sun, 28 Mar 2021 18:55:09 PDT (-0700), liu@jiuyang.me wrote:
> > This patch implements flush_cache_vmap and flush_cache_vunmap for
> > RISC-V, since these functions might modify PTE. Without this patch,
> > SFENCE.VMA won't be added to related codes, which might introduce a bug
> > in some out-of-order micro-architecture implementations.
> > 
> > Signed-off-by: Jiuyang Liu <liu@jiuyang.me>
> > ---
> > 
> >  arch/riscv/include/asm/cacheflush.h | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/arch/riscv/include/asm/cacheflush.h
> > b/arch/riscv/include/asm/cacheflush.h index 23ff70350992..4adf25248c43
> > 100644
> > --- a/arch/riscv/include/asm/cacheflush.h
> > +++ b/arch/riscv/include/asm/cacheflush.h
> > @@ -8,6 +8,14 @@
> > 
> >  #include <linux/mm.h>
> > 
> > +/*
> > + * flush_cache_vmap and flush_cache_vunmap might modify PTE, needs
> > SFENCE.VMA. + * - flush_cache_vmap is invoked after map_kernel_range()
> > has installed the page table entries. + * - flush_cache_vunmap is invoked
> > before unmap_kernel_range() deletes the page table entries
> These should have line breaks.
Fixed in the newest patch, thanks for pointing out.
> 
> > + */
> > +#define flush_cache_vmap(start, end) flush_tlb_all()
> 
> We shouldn't need cache flushes for permission upgrades: the ISA allows
> the old mappings to be visible until a fence, but the theory is that
> window will be sort for reasonable architectures so the overhead of
> flushing the entire TLB will overwhelm the extra faults.  There are a
> handful of places where we preemptively flush, but those are generally
> because we can't handle the faults correctly.
Got it, I removed this. 
> If you have some benchmark that demonstrates a performance issue on real
> hardware here then I'm happy to talk about this further, but this
> assumption is all over arch/riscv so I'd prefer to keep things
> consistent for now.
We are using riscv-boom + FireSim setting up a benchmark environment, I can 
try it after setting this.
> > +#define flush_cache_vunmap(start, end) flush_tlb_all()
> 
> This one does seem necessary.
> 
> > +
> > 
> >  static inline void local_flush_icache_all(void)
> >  {
> >  
> >  	asm volatile ("fence.i" ::: "memory");