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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id g14sm3223291pjh.28.2021.04.11.18.09.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Apr 2021 18:09:08 -0700 (PDT) Date: Sun, 11 Apr 2021 18:09:08 -0700 (PDT) X-Google-Original-Date: Sun, 11 Apr 2021 18:08:08 PDT (-0700) Subject: Re: [PATCH] riscv: keep interrupts disabled for BREAKPOINT exception In-Reply-To: <20210330021624.2b776386@xhacker> CC: Paul Walmsley , aou@eecs.berkeley.edu, guoren@linux.alibaba.com, mhiramat@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org From: Palmer Dabbelt To: jszhang3@mail.ustc.edu.cn Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 29 Mar 2021 11:16:24 PDT (-0700), jszhang3@mail.ustc.edu.cn wrote: > From: Jisheng Zhang > > Current riscv's kprobe handlers are run with both preemption and > interrupt enabled, this violates kprobe requirements. Fix this issue > by keeping interrupts disabled for BREAKPOINT exception. > > Fixes: c22b0bcb1dd0 ("riscv: Add kprobes supported") > Signed-off-by: Jisheng Zhang > --- > arch/riscv/kernel/entry.S | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S > index 744f3209c48d..4114b65698ec 100644 > --- a/arch/riscv/kernel/entry.S > +++ b/arch/riscv/kernel/entry.S > @@ -130,6 +130,8 @@ skip_context_tracking: > */ > andi t0, s1, SR_PIE > beqz t0, 1f > + li t0, EXC_BREAKPOINT > + beq s4, t0, 1f > #ifdef CONFIG_TRACE_IRQFLAGS > call trace_hardirqs_on > #endif This is on fixes, with a comment as otherwise I'm just going to forget why.