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[23.128.96.18]) by mx.google.com with ESMTP id h15si8194489ejq.438.2021.04.12.07.29.43; Mon, 12 Apr 2021 07:30:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ffwll.ch header.s=google header.b=QAGr8ID0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237806AbhDLO2o (ORCPT + 99 others); Mon, 12 Apr 2021 10:28:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238002AbhDLO2n (ORCPT ); Mon, 12 Apr 2021 10:28:43 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87C2BC06174A for ; Mon, 12 Apr 2021 07:28:23 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id r7so1175791wrm.1 for ; Mon, 12 Apr 2021 07:28:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=date:from:to:cc:subject:message-id:mail-followup-to:references :mime-version:content-disposition:in-reply-to; bh=5wosYuEdRDumEnBXzIheT9pdmOTpIyhQh146dwiPvB4=; b=QAGr8ID0S2S/RNKo79E6PW0g5QWI2bXQrRCfA47hGGFfP5iK/eKG1MgoDSol4c2N5w l8T3s5GycM4L7hCmrrCh6PNxzsc8FGe/XsEUFb4FW7HYxlyYUup2thYvTMx0N05KILVn VPfP9iMlglUOrdS3HZmHlfg84wZKvD4Cl4Bhk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id :mail-followup-to:references:mime-version:content-disposition :in-reply-to; bh=5wosYuEdRDumEnBXzIheT9pdmOTpIyhQh146dwiPvB4=; b=fvLtYwyfe7kckcNMByFHLHtk2I4zWq0gVNzGWVn1WD2uAHduoLAx/P2rMjxAdAyhRG yNA25lWZqa9FFQbp9jBWztaNOTg1nFFQgDyuGY8rktq3HAIx9RWZfna7NTNSc7515Pwf Yk58xn88O9rHczyHpJ12BePOpibPbXaUCEl2M4ONXhZFgzVS9M8641UW+kk+UTmwzK6s zPfwz8FFREpXOf58zjuA1/UHmYJoWc9LuSmc4m9TAT7BIv3HgaCkhDArNCpvtuQnKZjp yGMsCidwKxfQ4ZTzHKIRSGSfQHF4hBKv2eXPGDhKUXsdmA0hGLCQGAWkXrl00zfOMxXb YsdQ== X-Gm-Message-State: AOAM533AhBt/xcEpBf/rN3K13W5KdvksYdxiwxJfOBBCfTfhj9Kgw+e5 tvdN5T+aCTJV9cc2QWBLx/2F9w== X-Received: by 2002:a05:6000:1371:: with SMTP id q17mr23685250wrz.326.1618237702168; Mon, 12 Apr 2021 07:28:22 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:57f4:0:efd0:b9e5:5ae6:c2fa]) by smtp.gmail.com with ESMTPSA id g13sm21223836wrr.9.2021.04.12.07.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Apr 2021 07:28:21 -0700 (PDT) Date: Mon, 12 Apr 2021 16:28:19 +0200 From: Daniel Vetter To: Rob Clark Cc: dri-devel , Rob Clark , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , Jordan Crouse , "open list:DRM DRIVER FOR MSM ADRENO GPU" Subject: Re: [PATCH 0/8] drm/msm: Swappable GEM objects Message-ID: Mail-Followup-To: Rob Clark , dri-devel , Rob Clark , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , Jordan Crouse , "open list:DRM DRIVER FOR MSM ADRENO GPU" References: <20210405174532.1441497-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Operating-System: Linux phenom 5.7.0-1-amd64 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 08, 2021 at 08:23:42AM -0700, Rob Clark wrote: > On Thu, Apr 8, 2021 at 4:15 AM Daniel Vetter wrote: > > > > On Mon, Apr 05, 2021 at 10:45:23AM -0700, Rob Clark wrote: > > > From: Rob Clark > > > > > > One would normally hope not to be under enough memory pressure to need > > > to swap GEM objects to disk backed swap. But memory backed zram swap > > > (as enabled on chromebooks, for example) can actually be quite fast > > > and useful on devices with less RAM. On a 4GB device, opening up ~4 > > > memory intensive web pages (in separate windows rather than tabs, to try > > > and prevent tab discard), I see ~500MB worth of GEM objects, of which > > > maybe only 10% are active at any time, and with unpin/evict enabled, > > > only about half resident (which is a number that gets much lower if you > > > simulate extreme memory pressure). Assuming a 2:1 compression ratio (I > > > see a bit higher in practice, but cannot isolate swapped out GEM pages > > > vs other), that is like having an extra 100+MB of RAM, or more under > > > higher memory pressure. > > > > > > Rob Clark (8): > > > drm/msm: ratelimit GEM related WARN_ON()s > > > drm/msm: Reorganize msm_gem_shrinker_scan() > > > drm/msm: Clear msm_obj->sgt in put_pages() > > > drm/msm: Split iova purge and close > > > drm/msm: Add $debugfs/gem stats on resident objects > > > drm/msm: Track potentially evictable objects > > > drm/msm: Small msm_gem_purge() fix > > > drm/msm: Support evicting GEM objects to swap > > > > Given how much entertainement shrinkers are, should we aim for more common > > code here? > > > > Christian has tons of fun with adding something like this for ttm (well > > different shades of grey). i915 is going to adopt ttm, at least for > > discrete. > > > > The locking is also an utter pain, and msm seems to still live a lot in > > its own land here. I think as much as possible a standard approach here > > would be really good, ideally maybe as building blocks shared between ttm > > and gem-shmem drivers ... > > I don't disagree.. but also replacing the engines on an airplane > mid-flight isn't a great option either.. ;-) > > The hard part (esp. wrt to locking) is tracking the state of a given > bo.. ie. is it active, active+purgable, inactive+purgable, > inactive+unpinnable, etc. Currently the shmem helpers don't really > provide anything here. If they did, I suppose they could provide some > shrinker helpers as well. Unfortunately these days I barely have > enough time for drm/msm, let alone bolting this onto the shmem > helpers. I would recommend that if someone wanted to do this, that > they look at recent drm/msm shrinker patches that I've sent (ie. make > shrinker->count() lockless, and drop the locks in shrinker->scan() > body.. when the system is under heavy memory pressure, you start > getting shrinker called from all the threads so contention for mm_lock > can be a really bad problem) > > (Well, the other potential problem is that drm/msm has a lot of > different possible iommu pairings across the generations, so there is > some potential here to uncover exciting new bugs.. the locking at > least is the same for all the generations and pretty easy to test with > and without lockdep with some tests that push essentially all memory > into swap) So what we aimed for with i915 and discrete gpu is to first align on locking with dma_resv_lock for all buffer state, plus a bunch of lru/allocator locks for lists and stuff. And then with more aligned locking, figure out how to maybe share more code. The trouble is that right now neither shmem helpers, nor drivers using them, are really using dma_resv_lock to protect their per-buffer state. So yeah it's a bit an awkward situation, and I don't know myself really how to get out of it. Lack of people with tons of free time doesn't help much. So best case I think is that every time we touch helpers or drivers locking in a big way, we check whether it's at least slightly going towards dma_resv_lock or not. And at least make sure we're not going backwards, and maybe not spin wheels at standstill. I guess my question is, what would be good to have to make sure we at least all agree on the overall direction? -Daniel > > BR, > -R > > > -Daniel > > > > > > > > drivers/gpu/drm/msm/msm_drv.c | 2 +- > > > drivers/gpu/drm/msm/msm_drv.h | 13 ++- > > > drivers/gpu/drm/msm/msm_gem.c | 155 +++++++++++++++++-------- > > > drivers/gpu/drm/msm/msm_gem.h | 68 +++++++++-- > > > drivers/gpu/drm/msm/msm_gem_shrinker.c | 129 ++++++++++++-------- > > > drivers/gpu/drm/msm/msm_gpu_trace.h | 13 +++ > > > 6 files changed, 272 insertions(+), 108 deletions(-) > > > > > > -- > > > 2.30.2 > > > > > > _______________________________________________ > > > dri-devel mailing list > > > dri-devel@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > > > -- > > Daniel Vetter > > Software Engineer, Intel Corporation > > http://blog.ffwll.ch > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch