Received: by 2002:a05:6a10:17d3:0:0:0:0 with SMTP id hz19csp1829184pxb; Mon, 12 Apr 2021 07:40:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzR5FIavPzmK/m67XiHZ3OL/VO2Kyhi7DhB1NEtI46z58BBbzPgiLCcuMH+/raP36y08vVZ X-Received: by 2002:a17:906:80d1:: with SMTP id a17mr8200949ejx.55.1618238416407; Mon, 12 Apr 2021 07:40:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618238416; cv=none; d=google.com; s=arc-20160816; b=e67o8QsMsER5A+QckQCdddpjgFUNjLE7lBax0ioXupDGoSA0NrZQmQ7LODo2VPzAEy nj5FH5jEQuZTn4zgKFnK9y4dDpPV8FBENWNj7dxFRasfNvkmpkftE987ZQcL6qcxSeyk FOBrnvq8W4t171y4yvaQabdoenl1fzIgGUZfA4e1P/rvEI028hkkZTzKkDfZA9le+cdx VJJkoNtIoHQAylCK0oeuFmMnBzZ5HCzsv/B/TaiDyXqlJT/CZVxL7lKnN7EWX5NXZYoy zvb9gNtnEQXNvN1BoBkfJWGLNGsRf8N5OTYoRMWK/4uYc0zn6/up6uO+XLddYYiGyTDb JZpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:ironport-sdr:ironport-sdr; bh=T+bGbnxMaxuLL7kHPPB0L4axGbgwp5UFoNYoTzEJR/Y=; b=ZmOxeIZMvyKCeOcMcSPTMd7KGtqWhtQ77a2IQ4jMTr+x767cgK0DV/E9tZRMEKeAzC cqGeafpW//84jbjOPaL1F6CYHTHOSBGlaWPNdpcqdvfYyRxtlZj3cqNoeQ/bN9CWbHYs kd3Rg8Bu2SJo9F0KOpvbKDLUmqvXr0gmp3k3LSuzJZDavdVBm7uRasTB+L1HAw8zpgrN dtByG+FpL5Bxrha3IYFanYYmp5Qq85W1//XryZYYkmatgba7+4pKg4HxQ3Stfa7PbBVC b2KXsrOPMHohRCJjo3s6aL9g26o4USaQ/5Z0WQbNiCA6pV3CNvULHpaBS0LhJV2L1Dv1 rHPw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p3si8184264eds.157.2021.04.12.07.39.52; Mon, 12 Apr 2021 07:40:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242503AbhDLOjG (ORCPT + 99 others); Mon, 12 Apr 2021 10:39:06 -0400 Received: from mga09.intel.com ([134.134.136.24]:29206 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242393AbhDLOio (ORCPT ); Mon, 12 Apr 2021 10:38:44 -0400 IronPort-SDR: g2PTm1i/FR29I8/+v/XxJ3Vd26lLgSPd4OeHM/8pW/Yta0JgVfIPEcz39CdJ4mLzpStQ9aKOPH Razt2FWvxYgg== X-IronPort-AV: E=McAfee;i="6200,9189,9952"; a="194317974" X-IronPort-AV: E=Sophos;i="5.82,216,1613462400"; d="scan'208";a="194317974" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2021 07:38:25 -0700 IronPort-SDR: KwnJBnsn9ABGhSZ6s6KSU/iPPiBuQSakJ/8YgzMpZTYpHFddY5GnpjawKFBFewTDsf4J2RmAQQ mBU7AR/OZDrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,216,1613462400"; d="scan'208";a="398392793" Received: from otc-lr-04.jf.intel.com ([10.54.39.41]) by orsmga002.jf.intel.com with ESMTP; 12 Apr 2021 07:38:25 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org Cc: acme@kernel.org, tglx@linutronix.de, bp@alien8.de, namhyung@kernel.org, jolsa@redhat.com, ak@linux.intel.com, yao.jin@linux.intel.com, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, ricardo.neri-calderon@linux.intel.com, Kan Liang Subject: [PATCH V6 11/25] perf/x86/intel: Factor out intel_pmu_check_num_counters Date: Mon, 12 Apr 2021 07:30:51 -0700 Message-Id: <1618237865-33448-12-git-send-email-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618237865-33448-1-git-send-email-kan.liang@linux.intel.com> References: <1618237865-33448-1-git-send-email-kan.liang@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kan Liang Each Hybrid PMU has to check its own number of counters and mask fixed counters before registration. The intel_pmu_check_num_counters will be reused later to check the number of the counters for each hybrid PMU. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 38 ++++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index f727aa5..d7e2021 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5064,6 +5064,26 @@ static const struct attribute_group *attr_update[] = { static struct attribute *empty_attrs; +static void intel_pmu_check_num_counters(int *num_counters, + int *num_counters_fixed, + u64 *intel_ctrl, u64 fixed_mask) +{ + if (*num_counters > INTEL_PMC_MAX_GENERIC) { + WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", + *num_counters, INTEL_PMC_MAX_GENERIC); + *num_counters = INTEL_PMC_MAX_GENERIC; + } + *intel_ctrl = (1ULL << *num_counters) - 1; + + if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) { + WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", + *num_counters_fixed, INTEL_PMC_MAX_FIXED); + *num_counters_fixed = INTEL_PMC_MAX_FIXED; + } + + *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED; +} + __init int intel_pmu_init(void) { struct attribute **extra_skl_attr = &empty_attrs; @@ -5703,20 +5723,10 @@ __init int intel_pmu_init(void) x86_pmu.attr_update = attr_update; - if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { - WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", - x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); - x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; - } - x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1; - - if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { - WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", - x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); - x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; - } - - x86_pmu.intel_ctrl |= (u64)fixed_mask << INTEL_PMC_IDX_FIXED; + intel_pmu_check_num_counters(&x86_pmu.num_counters, + &x86_pmu.num_counters_fixed, + &x86_pmu.intel_ctrl, + (u64)fixed_mask); /* AnyThread may be deprecated on arch perfmon v5 or later */ if (x86_pmu.intel_cap.anythread_deprecated) -- 2.7.4