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Subject: Re: [PATCH] drm/ingenic: Fix pixclock rate for 24-bit serial panels
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From:   "H. Nikolaus Schaller" <hns@goldelico.com>
In-Reply-To: <VGGGRQ.1IX0AMZPBZBT3@crapouillou.net>
Date:   Mon, 12 Apr 2021 16:53:03 +0200
Cc:     David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
        Sam Ravnborg <sam@ravnborg.org>, od@zcrc.me,
        linux-mips@vger.kernel.org, dri-devel@lists.freedesktop.org,
        linux-kernel@vger.kernel.org, stable@vger.kernel.org
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Message-Id: <228D0565-DCFF-4314-A4AA-C58EBAD77D22@goldelico.com>
References: <20210323144008.166248-1-paul@crapouillou.net> <VGGGRQ.1IX0AMZPBZBT3@crapouillou.net>
To:     Paul Cercueil <paul@crapouillou.net>
Precedence: bulk


> Am 12.04.2021 um 16:34 schrieb Paul Cercueil <paul@crapouillou.net>:
>=20
> Hi,
>=20
> Can I have an ACK for this patch?
>=20
> Then I can apply it to drm-misc-next-fixes.
>=20
> Cheers,
> -Paul
>=20
>=20
> Le mar. 23 mars 2021 =E0 14:40, Paul Cercueil <paul@crapouillou.net> a =
=E9crit :
>> When using a 24-bit panel on a 8-bit serial bus, the pixel clock
>> requested by the panel has to be multiplied by 3, since the subpixels
>> are shifted sequentially.
>> The code (in ingenic_drm_encoder_atomic_check) already computed
>> crtc_state->adjusted_mode->crtc_clock accordingly, but clk_set_rate()
>> used crtc_state->adjusted_mode->clock instead.
>> Fixes: 28ab7d35b6e0 ("drm/ingenic: Properly compute timings when =
using a 3x8-bit panel")
>> Cc: stable@vger.kernel.org # v5.10

Tested-by: H. Nikolaus Schaller <hns@goldelico.com>	# CI20/jz4780 =
(HDMI) and Alpha400/jz4730 (LCD)

>> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
>> ---
>> drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>> diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c =
b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
>> index d60e1eefc9d1..cba68bf52ec5 100644
>> --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
>> +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
>> @@ -342,7 +342,7 @@ static void ingenic_drm_crtc_atomic_flush(struct =
drm_crtc *crtc,
>> 	if (priv->update_clk_rate) {
>> 		mutex_lock(&priv->clk_mutex);
>> 		clk_set_rate(priv->pix_clk,
>> -			     crtc_state->adjusted_mode.clock * 1000);
>> +			     crtc_state->adjusted_mode.crtc_clock * =
1000);
>> 		priv->update_clk_rate =3D false;
>> 		mutex_unlock(&priv->clk_mutex);
>> 	}
>> --
>> 2.30.2
>=20
>=20