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From:   =?UTF-8?Q?Christoph_M=C3=BCllner?= <christophm30@gmail.com>
Date:   Tue, 13 Apr 2021 11:22:40 +0200
Message-ID: <CAHB2gtTmGt=V4cUgbt3zGgi+y5h0f5ON0n+MdRC8P=su670qhQ@mail.gmail.com>
Subject: Re: [PATCH] riscv: locks: introduce ticket-based spinlock implementation
To:     Peter Zijlstra <peterz@infradead.org>
Cc:     Palmer Dabbelt <palmer@dabbelt.com>,
        Anup Patel <anup@brainfault.org>, Guo Ren <guoren@kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Guo Ren <guoren@linux.alibaba.com>, catalin.marinas@arm.com,
        will.deacon@arm.com, Arnd Bergmann <arnd@arndb.de>
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On Tue, Apr 13, 2021 at 10:03 AM Peter Zijlstra <peterz@infradead.org> wrot=
e:
>
> On Mon, Apr 12, 2021 at 11:54:55PM +0200, Christoph M=C3=BCllner wrote:
> > On Mon, Apr 12, 2021 at 7:33 PM Palmer Dabbelt <palmer@dabbelt.com> wro=
te:
>
> > > My plan is to add a generic ticket-based lock, which can be selected =
at
> > > compile time.  It'll have no architecture dependencies (though it'll
> > > likely have some hooks for architectures that can make this go faster=
).
> > > Users can then just pick which spinlock flavor they want, with the id=
ea
> > > being that smaller systems will perform better with ticket locks and
> > > larger systems will perform better with queued locks.  The main goal
> > > here is to give the less widely used architectures an easy way to hav=
e
> > > fair locks, as right now we've got a lot of code duplication because =
any
> > > architecture that wants ticket locks has to do it themselves.
> >
> > In the case of LL/SC sequences, we have a maximum of 16 instructions
> > on RISC-V. My concern with a pure-C implementation would be that
> > we cannot guarantee this (e.g. somebody wants to compile with -O0)
> > and I don't know of a way to abort the build in case this limit exceeds=
.
> > Therefore I have preferred inline assembly for OpenSBI (my initial idea
> > was to use closure-like LL/SC macros, where you can write the loop
> > in form of C code).
>
> For ticket locks you really only needs atomic_fetch_add() and
> smp_store_release() and an architectural guarantees that the
> atomic_fetch_add() has fwd progress under contention and that a sub-word
> store (through smp_store_release()) will fail the SC.
>
> Then you can do something like:
>
> void lock(atomic_t *lock)
> {
>         u32 val =3D atomic_fetch_add(1<<16, lock); /* SC, gives us RCsc *=
/
>         u16 ticket =3D val >> 16;
>
>         for (;;) {
>                 if (ticket =3D=3D (u16)val)
>                         break;
>                 cpu_relax();
>                 val =3D atomic_read_acquire(lock);
>         }
> }
>
> void unlock(atomic_t *lock)
> {
>         u16 *ptr =3D (u16 *)lock + (!!__BIG_ENDIAN__);
>         u32 val =3D atomic_read(lock);
>
>         smp_store_release(ptr, (u16)val + 1);
> }
>
> That's _almost_ as simple as a test-and-set :-) It isn't quite optimal
> on x86 for not being allowed to use a memop on unlock, since its being
> forced into a load-store because of all the volatile, but whatever.

What about trylock()?
I.e. one could implement trylock() without a loop, by letting
trylock() fail if the SC fails.
That looks safe on first view, but nobody does this right now.