Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII;
 format=flowed
Content-Transfer-Encoding: 7bit
Date:   Tue, 13 Apr 2021 14:26:36 +0200
From:   Michael Walle <michael@walle.cc>
To:     Ikjoon Jang <ikjn@chromium.org>
Cc:     linux-mtd@lists.infradead.org,
        Miquel Raynal <miquel.raynal@bootlin.com>,
        Pratyush Yadav <p.yadav@ti.com>,
        Richard Weinberger <richard@nod.at>,
        Tudor Ambarus <tudor.ambarus@microchip.com>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] mtd: spi-nor: macronix: Add block protection support to
 mx25u6435f
In-Reply-To: <20210413120210.3671536-1-ikjn@chromium.org>
References: <20210413120210.3671536-1-ikjn@chromium.org>
User-Agent: Roundcube Webmail/1.4.11
Message-ID: <51761f1db840c51bad17f5f275b4ce1a@walle.cc>
Precedence: bulk

Hi Ikjoon,

Am 2021-04-13 14:02, schrieb Ikjoon Jang:
> This patch adds block protection support to Macronix mx25u6432f and
> mx25u6435f. Two different chips share the same JEDEC ID while only
> mx25u6423f support section protections. And two chips have slightly
> different definitions of BP bits than generic (ST Micro) 
> implementation.

What is different compared to the current implementation? Could you give
an example?

> So this patch defines a new spi_nor_locking_ops only for macronix
> until this could be merged into a generic swp implementation.

TBH, I don't really like the code duplication and I'd presume that it
won't ever be merged with the generic code.

You also assume that both the WPSEL and T/B bit are 0, which might not
be true. Please note that both are write-once, thus should only be read.

See also:
https://lore.kernel.org/linux-mtd/346332bf6ab0dd92b9ffd9e126b6b97c@walle.cc/

-michael