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[193.12.47.89]) by smtp.gmail.com with ESMTPSA id q28sm3403883lfo.95.2021.04.13.07.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Apr 2021 07:40:26 -0700 (PDT) From: Tobias Waldekranz To: Marek Behun Cc: Vladimir Oltean , Ansuel Smith , netdev@vger.kernel.org, "David S. Miller" , Jakub Kicinski , Andrew Lunn , Vivien Didelot , Florian Fainelli , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Eric Dumazet , Wei Wang , Cong Wang , Taehee Yoo , =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= , zhang kai , Weilong Chen , Roopa Prabhu , Di Zhu , Francis Laniel , linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC net-next 0/3] Multi-CPU DSA support In-Reply-To: <20210413015450.1ae597da@thinkpad> References: <20210410133454.4768-1-ansuelsmth@gmail.com> <20210411200135.35fb5985@thinkpad> <20210411185017.3xf7kxzzq2vefpwu@skbuf> <878s5nllgs.fsf@waldekranz.com> <20210412213045.4277a598@thinkpad> <8735vvkxju.fsf@waldekranz.com> <20210412235054.73754df9@thinkpad> <87wnt7jgzk.fsf@waldekranz.com> <20210413005518.2f9b9cef@thinkpad> <87r1jfje26.fsf@waldekranz.com> <87o8ejjdu6.fsf@waldekranz.com> <20210413015450.1ae597da@thinkpad> Date: Tue, 13 Apr 2021 16:40:25 +0200 Message-ID: <87lf9mjlie.fsf@waldekranz.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 13, 2021 at 01:54, Marek Behun wrote: > On Tue, 13 Apr 2021 01:13:53 +0200 > Tobias Waldekranz wrote: > >> > ...you could get the isolation in place. But you will still lookup the >> > DA in the ATU, and there you will find a destination of either cpu0 or >> > cpu1. So for one of the ports, the destination will be outside of its >> > port based VLAN. Once the vectors are ANDed together, it is left with no >> > valid port to egress through, and the packet is dropped. >> > >> >> Am I wrong? I confess that I did not understand this into the most fine >> >> details, so it is entirely possible that I am missing something >> >> important and am completely wrong. Maybe this cannot be done. >> > >> > I really doubt that it can be done. Not in any robust way at >> > least. Happy to be proven wrong though! :) >> >> I think I figured out why it "works" for you. Since the CPU address is >> never added to the ATU, traffic for it is treated as unknown. Thanks to >> that, it flooded and the isolation brings it together. As soon as >> mv88e6xxx starts making use of Vladimirs offloading of host addresses >> though, I suspect this will fall apart. > > Hmm :( This is bad news. I would really like to make it balance via > input ports. The LAG balancing for this usecase is simply unacceptable, > since the switch puts so little information into the hash function. If you have the ports in standalone mode, you could imagine having each port use its own FID. But then you cannot to L2 forwarding between the LAN ports in hardware. If you have a chip with a TCAM, you could theoretically use that to get policy switching to the preferred CPU port. But since that would likely run on top of TC flower or something, it is not obvious to my how to would describe that kind of action. Barring something like that, I think you will have to accept the unacceptable :) > I will look into this, maybe ask some follow-up questions. > > Marek