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Subject: Re: [PATCH V3 2/2] perf/x86: Reset the dirty counter to prevent the
 leak for an RDPMC task
To:     Andy Lutomirski <luto@amacapital.net>
Cc:     Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@kernel.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Andi Kleen <ak@linux.intel.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Stephane Eranian <eranian@google.com>,
        Namhyung Kim <namhyung@kernel.org>
References: <1618340250-29027-1-git-send-email-kan.liang@linux.intel.com>
 <1618340250-29027-2-git-send-email-kan.liang@linux.intel.com>
 <CALCETrVVPzUd_hQ8xoomHn_wWRQJUvROeCt2do4_D4ROZoAVMg@mail.gmail.com>
From:   "Liang, Kan" <kan.liang@linux.intel.com>
Message-ID: <ced00596-20af-65b5-9e76-a23456215a64@linux.intel.com>
Date:   Tue, 13 Apr 2021 21:30:51 -0400
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On 4/13/2021 8:34 PM, Andy Lutomirski wrote:
> On Tue, Apr 13, 2021 at 12:05 PM <kan.liang@linux.intel.com> wrote:
>>
>> From: Kan Liang <kan.liang@linux.intel.com>
>>
>> The counter value of a perf task may leak to another RDPMC task.
>> For example, a perf stat task as below is running on CPU 0.
>>
>>      perf stat -e 'branches,cycles' -- taskset -c 0 ./workload
> 
> I assume this doesn't fix the leak if the sensitive counter is systemwide?
>

Right.

> Could Intel please add proper security and ideally virtualization for
> this?  Ideally RDPMC permission would be a bitmask for all RDPMC-able
> counters, not just a single on/off switch.
> 

Yes, we are working on it.

For now, I think this patch is what we can do so far.

Thanks,
Kan