Received: by 2002:a05:6a10:17d3:0:0:0:0 with SMTP id hz19csp21350pxb; Wed, 14 Apr 2021 08:31:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwb1/9MufIvWD3vEVl+LPwPWgWI/0PG0qcovbcoXQpEH3HpVjkkOne7GJ8tsoZihRZoAHZo X-Received: by 2002:a17:907:3ac1:: with SMTP id fi1mr23711027ejc.139.1618414305441; Wed, 14 Apr 2021 08:31:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618414305; cv=none; d=google.com; s=arc-20160816; b=gja+n+V/5c8gpbK4q2EK6gBgxytYJIt5Q1mr4sOqDF5hwz2qYcKyeG2iPQ3K+LEK8i fArUAhvQuOfZsNWp7OYE9y8FhI8axcbdLruBZLtHo4TrWV/SZBUtcuzQGibhWlV1h/jG nbeLi1YHA9QHerV2bZtZouMhrGWpDEszohIxwN9RQTub6bcBU7IrtcEn1BWXgS63Sp0v y2iK6phhsTf0ALVtZLjljtT/cpWCnIMnAf8Vg+I5yfpF3h3O3P1qQv1WmBhasNwSZ1Vo gUOwz6TDgUWFWE1GFAMtOSuSGIxDI/nRAzJ/yN9LFeBKeQbUX0AUw/y99GBq8dSSgCgS P6qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=1M7zwzlivTWq9usFcQMcCwgoSW1+2fSL3f3eakwqc6w=; b=Xa0pJ0nau04/9Z7Gh7c5gZ0ZLtU5FC8araArZshzOLbuZSghNNXmFtukOnGgh1JDqE XlHUMg9tdEIVjF41jYe/KY6O9PnFjAQyyZnokkz+4lY2rtaoWRh9LJTDsKQnMM5MSE2G 1MuRtH4GroNPPxqdaYPqaiezRUUloK6sVvHFOJZPY0e1+Mnb1fMJEq5hHdydusyZ6Csj prTx/72HbPaNJzKGYdkG9d0PjQsckxY9wYjIQ6WubEw3TkBFDyZw9c8ApaSPr1+18vkY RNzwMdCBkjaQYRDNWt1qmga3zBqO+PECC65p9M1ZXLdNtg5lhxzQOzYxGIB4InXv6JVb oLAQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=huawei.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a62si12873151edf.180.2021.04.14.08.31.14; Wed, 14 Apr 2021 08:31:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=huawei.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350483AbhDNL0D (ORCPT + 99 others); Wed, 14 Apr 2021 07:26:03 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:16459 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350205AbhDNLZV (ORCPT ); Wed, 14 Apr 2021 07:25:21 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FL0Sf33jKztW1h; Wed, 14 Apr 2021 19:22:42 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.47.82.32) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Wed, 14 Apr 2021 19:24:47 +0800 From: Shameer Kolothum To: , , CC: , , , , , , , , Subject: [PATCH v4 06/16] arm64/mm: Introduce NUM_CTXT_ASIDS Date: Wed, 14 Apr 2021 12:23:02 +0100 Message-ID: <20210414112312.13704-7-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20210414112312.13704-1-shameerali.kolothum.thodi@huawei.com> References: <20210414112312.13704-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.47.82.32] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Julien Grall At the moment ASID_FIRST_VERSION is used to know the number of ASIDs supported. As we are going to move the ASID allocator to a separate file, it would be better to use a different name for external users. Signed-off-by: Julien Grall Signed-off-by: Shameer Kolothum --- v3-->v4 -Dropped patch #6, but retained the name NUM_CTXT_ASIDS. --- arch/arm64/mm/context.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 628304e0d3b1..0f11d7c7f6a3 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -41,9 +41,9 @@ static unsigned long nr_pinned_asids; static unsigned long *pinned_asid_map; #define ASID_MASK(info) (~GENMASK((info)->bits - 1, 0)) -#define ASID_FIRST_VERSION(info) (1UL << (info)->bits) +#define NUM_CTXT_ASIDS(info) (1UL << ((info)->bits)) +#define ASID_FIRST_VERSION(info) NUM_CTXT_ASIDS(info) -#define NUM_USER_ASIDS(info) ASID_FIRST_VERSION(info) #define asid2idx(info, asid) ((asid) & ~ASID_MASK(info)) #define idx2asid(info, idx) asid2idx(info, idx) @@ -87,7 +87,7 @@ void verify_cpu_asid_bits(void) static void set_kpti_asid_bits(struct asid_info *info, unsigned long *map) { - unsigned int len = BITS_TO_LONGS(NUM_USER_ASIDS(info)) * sizeof(unsigned long); + unsigned int len = BITS_TO_LONGS(NUM_CTXT_ASIDS(info)) * sizeof(unsigned long); /* * In case of KPTI kernel/user ASIDs are allocated in * pairs, the bottom bit distinguishes the two: if it @@ -100,11 +100,11 @@ static void set_kpti_asid_bits(struct asid_info *info, unsigned long *map) static void set_reserved_asid_bits(struct asid_info *info) { if (pinned_asid_map) - bitmap_copy(info->map, pinned_asid_map, NUM_USER_ASIDS(info)); + bitmap_copy(info->map, pinned_asid_map, NUM_CTXT_ASIDS(info)); else if (arm64_kernel_unmapped_at_el0()) set_kpti_asid_bits(info, info->map); else - bitmap_clear(info->map, 0, NUM_USER_ASIDS(info)); + bitmap_clear(info->map, 0, NUM_CTXT_ASIDS(info)); } #define asid_gen_match(asid, info) \ @@ -204,8 +204,8 @@ static u64 new_context(struct asid_info *info, atomic64_t *pasid, * a reserved TTBR0 for the init_mm and we allocate ASIDs in even/odd * pairs. */ - asid = find_next_zero_bit(info->map, NUM_USER_ASIDS(info), info->map_idx); - if (asid != NUM_USER_ASIDS(info)) + asid = find_next_zero_bit(info->map, NUM_CTXT_ASIDS(info), info->map_idx); + if (asid != NUM_CTXT_ASIDS(info)) goto set_asid; /* We're out of ASIDs, so increment the global generation count */ @@ -214,7 +214,7 @@ static u64 new_context(struct asid_info *info, atomic64_t *pasid, flush_context(info); /* We have more ASIDs than CPUs, so this will always succeed */ - asid = find_next_zero_bit(info->map, NUM_USER_ASIDS(info), 1); + asid = find_next_zero_bit(info->map, NUM_CTXT_ASIDS(info), 1); set_asid: __set_bit(asid, info->map); @@ -387,7 +387,7 @@ void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm) static int asids_update_limit(void) { struct asid_info *info = &asid_info; - unsigned long num_available_asids = NUM_USER_ASIDS(info); + unsigned long num_available_asids = NUM_CTXT_ASIDS(info); if (arm64_kernel_unmapped_at_el0()) { num_available_asids /= 2; @@ -418,18 +418,18 @@ static int asids_init(void) info->bits = get_cpu_asid_bits(); atomic64_set(&info->generation, ASID_FIRST_VERSION(info)); - info->map = kcalloc(BITS_TO_LONGS(NUM_USER_ASIDS(info)), + info->map = kcalloc(BITS_TO_LONGS(NUM_CTXT_ASIDS(info)), sizeof(*info->map), GFP_KERNEL); if (!info->map) panic("Failed to allocate bitmap for %lu ASIDs\n", - NUM_USER_ASIDS(info)); + NUM_CTXT_ASIDS(info)); info->map_idx = 1; info->active = &active_asids; info->reserved = &reserved_asids; raw_spin_lock_init(&info->lock); - pinned_asid_map = kcalloc(BITS_TO_LONGS(NUM_USER_ASIDS(info)), + pinned_asid_map = kcalloc(BITS_TO_LONGS(NUM_CTXT_ASIDS(info)), sizeof(*pinned_asid_map), GFP_KERNEL); nr_pinned_asids = 0; -- 2.17.1